| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <568537C3.3060902@huawei.com>
Date: Thu, 31 Dec 2015 22:12:19 +0800
From: Rongrong Zou <zourongrong@...wei.com>
To: Arnd Bergmann <arnd@...db.de>, Rongrong Zou <zourongrong@...il.com>
CC: <minyard@....org>, <gregkh@...uxfoundation.org>,
<catalin.marinas@....com>, <will.deacon@....com>,
<linuxarm@...wei.com>, <linux-kernel@...r.kernel.org>,
<benh@...nel.crashing.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH v1 3/3] ARM64 LPC: update binding doc
Sorry for so late reply, it is difficult for me to understand ISA config :( .
在 2015/12/30 17:06, Arnd Bergmann 写道:
> On Tuesday 29 December 2015 21:33:52 Rongrong Zou wrote:
>> Signed-off-by: Rongrong Zou <zourongrong@...il.com>
>> ---
>> .../devicetree/bindings/arm64/low-pin-count.txt | 20 ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm64/low-pin-count.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm64/low-pin-count.txt b/Documentation/devicetree/bindings/arm64/low-pin-count.txt
>> new file mode 100644
>> index 0000000..215f2c4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm64/low-pin-count.txt
>> @@ -0,0 +1,20 @@
>> +Low Pin Count bus driver
>> +
>> +Usually LPC controller is part of PCI host bridge, so the legacy ISA
>> +port locate on LPC bus can be accessed directly. But some SoC have
>> +independent LPC controller, and we can access the legacy port by specifying
>> +LPC address cycle. Thus, LPC driver is introduced.
>> +
>> +Required properties:
>> +- compatible: "low-pin-count"
>> +- reg: specifies low pin count address range
>> +
>> +
>> +Example:
>> +
>> + lpc_0: lpc@...b0000 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "low-pin-count";
>> + reg = <0x0 0xa01b0000 0x0 0x10000>;
>> + };
>
> One more thought: please try to stick as closely as possible to the existing
> ISA binding that is documented at
>
> http://www.firmware.org/1275/bindings/isa/isa0_4d.ps
From the specification, I think I should use 2 32bit integer to describe the isa addr in dts.
>
> In particular, this should cover the possibility of describing both memory
> and I/O spaces in child devices.
>
I found below config in powerpc dts "arch/powerpc/boot/dts/mpc8544ds.dts"
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <0xf000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x1000000 0x0 0x0
0x1000>;
interrupt-parent = <&i8259>;
rtc@70 {
compatible = "pnpPNP,b00";
reg = <0x1 0x70 0x2>;
};
the isa space in child-node: reg = <0x1 0x70 0x2>;
0x1 means IO space, 70 means addr, 0x2 is size.
but when i config the following in dts, the ipmi_0 node can't be probed,
I think there may be some problems.
lpc_0: lpc@...b0000 {
compatible = "low-pin-count";
device_type = "isa";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xa01b0000 0x0 0x10000>;
ipmi_0:ipmi@...000e4{
device_type = "ipmi";
compatible = "ipmi-bt";
reg = <0x1 0x000000e4 0x4>;
};
> Arnd
> _______________________________________________
> linuxarm mailing list
> linuxarm@...wei.com
> http://rnd-openeuler.huawei.com/mailman/listinfo/linuxarm
>
>
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists