lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1451881723-2478-15-git-send-email-milo.kim@ti.com>
Date:	Mon, 4 Jan 2016 13:28:38 +0900
From:	Milo Kim <milo.kim@...com>
To:	<tglx@...utronix.de>
CC:	<jason@...edaemon.net>, <marc.zyngier@....com>,
	<alexandre.belloni@...e-electrons.com>,
	<boris.brezillon@...e-electrons.com>,
	<ludovic.desroches@...el.com>, <nicolas.ferre@...el.com>,
	<linux-kernel@...r.kernel.org>, Milo Kim <milo.kim@...com>
Subject: [PATCH 14/19] irqchip: atmel-aic: add common HW init function

AIC and AIC5 have common interrupt initialization process.
With aic_reg_data configuration, chip specific init functions can be
combined into one function, aic_common_hw_init().

Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Jason Cooper <jason@...edaemon.net>
Cc: Marc Zyngier <marc.zyngier@....com>
Cc: Alexandre Belloni <alexandre.belloni@...e-electrons.com>
Cc: Boris BREZILLON <boris.brezillon@...e-electrons.com>
Cc: Ludovic Desroches <ludovic.desroches@...el.com>
Cc: Nicolas Ferre <nicolas.ferre@...el.com>
Cc: linux-kernel@...r.kernel.org
Signed-off-by: Milo Kim <milo.kim@...com>
---
 drivers/irqchip/irq-atmel-aic-common.c | 42 ++++++++++++++++++++++++++++++++++
 drivers/irqchip/irq-atmel-aic.c        | 31 -------------------------
 drivers/irqchip/irq-atmel-aic5.c       | 32 --------------------------
 3 files changed, 42 insertions(+), 63 deletions(-)

diff --git a/drivers/irqchip/irq-atmel-aic-common.c b/drivers/irqchip/irq-atmel-aic-common.c
index 777cf33..67f9204 100644
--- a/drivers/irqchip/irq-atmel-aic-common.c
+++ b/drivers/irqchip/irq-atmel-aic-common.c
@@ -24,6 +24,8 @@
 
 #include "irq-atmel-aic-common.h"
 
+#define NR_AIC_IRQS			32
+
 #define AT91_AIC_SMR_BASE		0
 #define AT91_AIC_SVR_BASE		0x80
 #define AT91_AIC_IVR			0x100
@@ -431,6 +433,45 @@ static void __init aic_common_ext_irq_of_init(struct irq_domain *domain)
 	}
 }
 
+static void __init aic_hw_init(struct irq_domain *domain)
+{
+	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
+	int i;
+
+	/*
+	 * Perform 8 End Of Interrupt Command to make sure AIC
+	 * will not Lock out nIRQ
+	 */
+	for (i = 0; i < 8; i++)
+		irq_reg_writel(gc, 0, aic_reg_data->eoi);
+
+	/*
+	 * Spurious Interrupt ID in Spurious Vector Register.
+	 * When there is no current interrupt, the IRQ Vector Register
+	 * reads the value stored in AIC_SPU
+	 */
+	irq_reg_writel(gc, 0xffffffff, aic_reg_data->spu);
+
+	/* No debugging in AIC: Debug (Protect) Control Register */
+	irq_reg_writel(gc, 0, aic_reg_data->dcr);
+
+	/* Disable and clear all interrupts initially */
+	if (aic_is_ssr_used()) {
+		for (i = 0; i < domain->revmap_size; i++) {
+			irq_reg_writel(gc, i, aic_reg_data->ssr);
+			irq_reg_writel(gc, i, aic_reg_data->svr);
+			irq_reg_writel(gc, 1, aic_reg_data->idcr);
+			irq_reg_writel(gc, 1, aic_reg_data->iccr);
+		}
+	} else {
+		irq_reg_writel(gc, 0xffffffff, aic_reg_data->idcr);
+		irq_reg_writel(gc, 0xffffffff, aic_reg_data->iccr);
+
+		for (i = 0; i < NR_AIC_IRQS; i++)
+			irq_reg_writel(gc, i, aic_reg_data->svr + (i * 4));
+	}
+}
+
 struct irq_domain *__init aic_common_of_init(struct device_node *node,
 					     const char *name, int nirqs)
 {
@@ -492,6 +533,7 @@ struct irq_domain *__init aic_common_of_init(struct device_node *node,
 	}
 
 	aic_common_ext_irq_of_init(domain);
+	aic_hw_init(domain);
 
 	return domain;
 
diff --git a/drivers/irqchip/irq-atmel-aic.c b/drivers/irqchip/irq-atmel-aic.c
index 721ecb6..ef2cfb8 100644
--- a/drivers/irqchip/irq-atmel-aic.c
+++ b/drivers/irqchip/irq-atmel-aic.c
@@ -74,36 +74,6 @@ aic_handle(struct pt_regs *regs)
 		handle_domain_irq(aic_domain, irqnr, regs);
 }
 
-static void __init aic_hw_init(struct irq_domain *domain)
-{
-	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
-	int i;
-
-	/*
-	 * Perform 8 End Of Interrupt Command to make sure AIC
-	 * will not Lock out nIRQ
-	 */
-	for (i = 0; i < 8; i++)
-		irq_reg_writel(gc, 0, AT91_AIC_EOICR);
-
-	/*
-	 * Spurious Interrupt ID in Spurious Vector Register.
-	 * When there is no current interrupt, the IRQ Vector Register
-	 * reads the value stored in AIC_SPU
-	 */
-	irq_reg_writel(gc, 0xffffffff, AT91_AIC_SPU);
-
-	/* No debugging in AIC: Debug (Protect) Control Register */
-	irq_reg_writel(gc, 0, AT91_AIC_DCR);
-
-	/* Disable and clear all interrupts initially */
-	irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
-	irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
-
-	for (i = 0; i < NR_AIC_IRQS; i++)
-		irq_reg_writel(gc, i, AT91_AIC_SVR(i));
-}
-
 static int __init aic_of_init(struct device_node *node,
 			      struct device_node *parent)
 {
@@ -117,7 +87,6 @@ static int __init aic_of_init(struct device_node *node,
 		return PTR_ERR(domain);
 
 	aic_domain = domain;
-	aic_hw_init(domain);
 	set_handle_irq(aic_handle);
 
 	return 0;
diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
index ff487089..4551bf6 100644
--- a/drivers/irqchip/irq-atmel-aic5.c
+++ b/drivers/irqchip/irq-atmel-aic5.c
@@ -83,37 +83,6 @@ aic5_handle(struct pt_regs *regs)
 		handle_domain_irq(aic5_domain, irqnr, regs);
 }
 
-static void __init aic5_hw_init(struct irq_domain *domain)
-{
-	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
-	int i;
-
-	/*
-	 * Perform 8 End Of Interrupt Command to make sure AIC
-	 * will not Lock out nIRQ
-	 */
-	for (i = 0; i < 8; i++)
-		irq_reg_writel(gc, 0, AT91_AIC5_EOICR);
-
-	/*
-	 * Spurious Interrupt ID in Spurious Vector Register.
-	 * When there is no current interrupt, the IRQ Vector Register
-	 * reads the value stored in AIC_SPU
-	 */
-	irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU);
-
-	/* No debugging in AIC: Debug (Protect) Control Register */
-	irq_reg_writel(gc, 0, AT91_AIC5_DCR);
-
-	/* Disable and clear all interrupts initially */
-	for (i = 0; i < domain->revmap_size; i++) {
-		irq_reg_writel(gc, i, AT91_AIC5_SSR);
-		irq_reg_writel(gc, i, AT91_AIC5_SVR);
-		irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
-		irq_reg_writel(gc, 1, AT91_AIC5_ICCR);
-	}
-}
-
 static int __init aic5_of_init(struct device_node *node,
 			       struct device_node *parent,
 			       int nirqs)
@@ -131,7 +100,6 @@ static int __init aic5_of_init(struct device_node *node,
 		return PTR_ERR(domain);
 
 	aic5_domain = domain;
-	aic5_hw_init(domain);
 	set_handle_irq(aic5_handle);
 
 	return 0;
-- 
2.6.4

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ