linux-kernel - Re: [PATCH 1/3] ASoC: fsl_ssi: mark SACNT register volatile

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Message-ID: <5692CE43.20708@tabi.org>
Date:	Sun, 10 Jan 2016 15:33:55 -0600
From:	Timur Tabi <timur@...i.org>
To:	"Maciej S. Szmigiero" <mail@...iej.szmigiero.name>,
	"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>
Cc:	Nicolin Chen <nicoleotsuka@...il.com>,
	Xiubo Li <Xiubo.Lee@...il.com>,
	Liam Girdwood <lgirdwood@...il.com>,
	Mark Brown <broonie@...nel.org>,
	"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
	linux-kernel <linux-kernel@...r.kernel.org>,
	Fabio Estevam <festevam@...il.com>
Subject: Re: [PATCH 1/3] ASoC: fsl_ssi: mark SACNT register volatile

Maciej S. Szmigiero wrote:
> +	regmap_write(regs, CCSR_SSI_SACNT,
> +			ssi_private->regcache_sacnt);

So I'm not familiar with all of the regcache features, but I understand 
this patch.  I was wondering if it makes sense to write the same exact 
value that was read previously.  Isn't it possible for the WR or RD bits 
to change between fsl_ssi_suspend() and fsl_ssi_resume()?  That is, 
should we be doing this instead?

u32 temp;
regmap_read(regs, CCSR_SSI_SACNT, &temp);
temp &= 0x18; // preserve WR and RD
regmap_write(regs, CCSR_SSI_SACNT, (ssi_private->regcache_sacnt & ~0x18) 
| temp);