[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20160115111435.GE25104@pd.tnic>
Date: Fri, 15 Jan 2016 12:14:35 +0100
From: Borislav Petkov <bp@...en8.de>
To: Aravind Gopalakrishnan <aravind.gopalakrishnan@....com>
Cc: tony.luck@...el.com, tglx@...utronix.de, mingo@...hat.com,
hpa@...or.com, x86@...nel.org, linux-edac@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/5] x86/mcheck/AMD: Reduce number of blocks scanned per
bank
On Thu, Jan 14, 2016 at 05:08:30PM -0600, Aravind Gopalakrishnan wrote:
> In the same manner, we'd still have to know the last possible MISC
> register for future processors..
I was going to suggest that we should probably *count* the MISC
registers upfront so that we know exactly how many are we dealing with
instead of relying on macros but that would be overengineering it for no
good reason. And we're checking the valid bits and so on, so we're good.
So ok, I'm persuaded.
Thanks.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
Powered by blists - more mailing lists