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Message-ID: <56982B89.6080206@amd.com>
Date:	Thu, 14 Jan 2016 17:13:13 -0600
From:	Aravind Gopalakrishnan <aravind.gopalakrishnan@....com>
To:	Borislav Petkov <bp@...en8.de>
CC:	<tony.luck@...el.com>, <tglx@...utronix.de>, <mingo@...hat.com>,
	<hpa@...or.com>, <x86@...nel.org>, <linux-edac@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 5/5] x86/mcheck/AMD: Set MCAX Enable bit

On 1/14/2016 4:58 PM, Borislav Petkov wrote:
> On Thu, Jan 14, 2016 at 04:53:58PM -0600, Aravind Gopalakrishnan wrote:
>> Well McaX is name of the field in the MSR. I retained the "SMCA" prefix as
> What does that McaX mean, btw?

McaX indicates-
* we have MCA MSRs in a new address range
* there are more registers per bank (hence the definitions to registers 
like MCx_IPID, MCx_CONFIG etc)


>> these are all still part of the ScalableMCA changes.
>> I would prefer if "MCAX" is retained as it is indicative of which bit we are
>> touching. So how about just MCAX_EN_OFF ?
> If we're going to have a bunch of defines belonging to SMCA, then we're
> better having them all start with SMCA_ after all, I guess.
>
> But please make sure you have comments over their definitions explaining
> what those bits are. When an outsider is reading those patches and SMCA,
> MCAX start appearing left and right, his head most likely starts to
> spin.
>

Sure, I shall add some comments around the definitions for V2.

Thanks,
-Aravind.

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