linux-kernel - [PATCH V2 0/5] Updates to AMD MCE driver per Scalable MCA spec

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-ID: <1452901836-27632-1-git-send-email-Aravind.Gopalakrishnan@amd.com>
Date:	Fri, 15 Jan 2016 17:50:31 -0600
From:	Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
To:	<tony.luck@...el.com>, <bp@...en8.de>, <tglx@...utronix.de>,
	<mingo@...hat.com>, <hpa@...or.com>
CC:	<x86@...nel.org>, <linux-edac@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
Subject: [PATCH V2 0/5] Updates to AMD MCE driver per Scalable MCA spec

The patchset contains updates to the MCE driver based
on the Scalable MCA specification.

Patches 1-3 include some minor changes to existing code
and have been tested for regressions on older families.

Patches 4-5 is new code and only runs on processors
with ScalableMCA feature enabled (for future)

Patch 1: Order of mce_amd_feature_init() was incorrect as
	 it should be called after we gather features from
	 cpuid bits. Fixing that in this patch
Patch 2: We do not require shared bank verification on ZP.
	 Modifying code here to return early if we are on a processor
	 that supports SMCA feature.
Patch 3: The number of blocks per bank is reduced from Fam17h onwards.
	 Fixing code to reflect this architectural change
Patch 4: LVT offset for thresholding is now programmed in different MSR
	 as opposed to per-bank MISC register in earlier processors.
	 Fixing code here to obtain LVT offset from correct MSR.
Patch 5: OS is required to set MCAXEn bit in the per-bank CONFIG MSR
	 to acknowledge the use of new MSR range for MCA.
	 Doing that here and also creating definitions for the new
	 MSR range in msr-index.

Changes in V2 (per Boris)
  - Include only definitions on header file that we are using here
  - Add comments around macros that belong to SMCA

Aravind Gopalakrishnan (5):
  x86, mce: Fix order of AMD MCE init function call
  x86/mcheck/AMD: Do not perform shared bank check for future processors
  x86/mcheck/AMD: Reduce number of blocks scanned per bank
  x86/mcheck/AMD: Fix LVT offset configuration for thresholding
  x86/mcheck/AMD: Set MCAX Enable bit

 arch/x86/include/asm/msr-index.h     |  5 +++
 arch/x86/kernel/cpu/mcheck/mce.c     |  2 +-
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 63 ++++++++++++++++++++++++++++++++++--
 3 files changed, 67 insertions(+), 3 deletions(-)

-- 
2.7.0