linux-kernel - Re: [RFC PATCH v2] Add IPI entry for CPU UP

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Date:	Fri, 22 Jan 2016 08:07:08 +0000
From:	Marc Zyngier <marc.zyngier@....com>
To:	Zhaoyang Huang <zhaoyang.huang@...aro.org>
Cc:	Mark Rutland <mark.rutland@....com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
	"Zhaoyang Huang (黄朝阳)" 
	<zhaoyang.huang@...eadtrum.com>,
	Catalin Marinas <catalin.marinas@....com>, will.deacon@....com,
	linux-kernel@...r.kernel.org, Hanjun Guo <hanjun.guo@...aro.org>,
	suzuki.poulose@....com
Subject: Re: [RFC PATCH v2] Add IPI entry for CPU UP

On Fri, 22 Jan 2016 10:01:24 +0800
Zhaoyang Huang <zhaoyang.huang@...aro.org> wrote:

> On 21 January 2016 at 18:51, Mark Rutland <mark.rutland@....com>
> wrote:
> > On Thu, Jan 21, 2016 at 04:48:57PM +0800, Zhaoyang Huang wrote:
> >> Hi Mark,
> >
> > Hi,
> >
> >> Do you have any suggestion on how to sync the GIC operation from
> >> kernel and psci parallelly? Thanks!
> >
> > I'm not sure what you mean.
> >
> > What problem are you having with synchronising GIC accesses?
> >
> > As far as I can see, the CPU sending the IPI can simply poke the
> > relevant register in the distributor without requiring any
> > synchronisation. The CPU receiving the IPI is the only CPU with
> > access to its CPU interface.
> >
> > Could you describe your problem in more detail?
> >
> > Thanks,
> > Mark.
> >
> Hi Mark,
> Sorry for making confusions. I mean mutex between kernel and trustzone
> when accessing
> GIC registers. It is possible for they two issuing an accessing to the
> same register at the
> same time. How should I handle such kind of race conditions?

The GIC programming interface is designed to allow this kind of access
without locking:

- CPU interface: the CPU cannot be in secure and non-secure at the same
  time, so there is no race for the access. Furthermore, the fact that
  secure interrupts have a higher priority than non-secure ones ensure
  that a secure interrupt will preempt a non-secure one, making the
  whole thing race free.

- Distributor: Writing to the GICD_SGIR register is atomic, and the GIC
  will ensure simultaneous access.

In a nutshell, there is no need to worry about these things, because
the GIC architecture has been designed from the ground up to support
this.

See for example this:
http://git.denx.de/?p=u-boot.git;a=blob_plain;f=arch/arm/cpu/armv7/sunxi/psci_sun7i.S;hb=HEAD

which uses IPIs to implement PSCI on an existing ARMv7 system.

Thanks,

	M.
-- 
Without deviation from the norm, progress is not possible.