linux-kernel - Re: [PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

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Date:	Tue, 2 Feb 2016 14:44:26 +0800
From:	Chen-Yu Tsai <wens@...e.org>
To:	Vishnu Patekar <vishnupatekar0510@...il.com>
Cc:	Rob Herring <robh+dt@...nel.org>, Jonathan Corbet <corbet@....net>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Maxime Ripard <maxime.ripard@...e-electrons.com>,
	Russell King - ARM Linux <linux@....linux.org.uk>,
	Emilio Lopez <emilio@...pez.com.ar>,
	Jens Kuske <jenskuske@...il.com>,
	Hans De Goede <hdegoede@...hat.com>,
	Chen-Yu Tsai <wens@...e.org>,
	devicetree <devicetree@...r.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
	linux-kernel <linux-kernel@...r.kernel.org>,
	linux-sunxi <linux-sunxi@...glegroups.com>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Reinder de Haan <patchesrdh@...as.com>,
	linux-clk <linux-clk@...r.kernel.org>
Subject: Re: [PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
<vishnupatekar0510@...il.com> wrote:
> This adds A83T PRCM related clocks, clock resets.
>
> As a83t apb0 gates clock support is added earlier, this enables it.
> Apart from apb0 gates, other added clocks are compatible with
> earlier sun8i socs.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@...il.com>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index ac96aa1..5ea20ff 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -268,6 +268,44 @@
>                                              "mmc2_output",
>                                              "mmc2_sample";
>                 };
> +
> +               cpus_clk: clk@...01400 {
> +                       compatible = "allwinner,sun9i-a80-cpus-clk";
> +                       reg = <0x01f01400 0x4>;
> +                       #clock-cells = <0>;
> +                       clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
> +                       clock-output-names = "cpus";
> +               };
> +
> +               ahb0: ahb0_clk {
> +                       compatible = "fixed-factor-clock";
> +                       #clock-cells = <0>;
> +                       clock-div = <1>;
> +                       clock-mult = <1>;
> +                       clocks = <&cpus_clk>;
> +                       clock-output-names = "ahb0";
> +               };
> +
> +               apb0: clk@...0140c {
> +                       compatible = "allwinner,sun8i-a23-apb0-clk";

This is actually wrong, as it is wrong in sun9i-a80.dtsi.
I've sent a patch series for it.

Also the drivers for "allwinner,sun9i-a80-cpus-clk" and
"allwinner,sun9i-a80-apbs-clk"
are only compiled for CONFIG_MACH_SUN9I. Please add a patch to address this.

Regards
ChenYu

> +                       reg = <0x01f0140c 0x4>;
> +                       #clock-cells = <0>;
> +                       clocks = <&ahb0>;
> +                       clock-output-names = "apb0";
> +               };
> +
> +               apb0_gates: clk@...01428 {
> +                       compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
> +                       reg = <0x01f01428 0x4>;
> +                       #clock-cells = <1>;
> +                       clocks = <&apb0>;
> +                       clock-indices = <0>, <1>,
> +                                       <2>, <3>,
> +                                       <4>, <6>, <7>;
> +                       clock-output-names = "apb0_pio", "apb0_ir",
> +                                       "apb0_timer", "apb0_rsb",
> +                                       "apb0_uart", "apb0_i2c0", "apb0_twd";
> +               };
>         };
>
>         soc {
> @@ -434,5 +472,11 @@
>                         #interrupt-cells = <3>;
>                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>                 };
> +
> +               apb0_reset: reset@...014b0 {
> +                       reg = <0x01f014b0 0x4>;
> +                       compatible = "allwinner,sun6i-a31-clock-reset";
> +                       #reset-cells = <1>;
> +               };
>         };
>  };
> --
> 1.9.1
>