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Message-ID: <20160205140259.72a33699@free-electrons.com>
Date: Fri, 5 Feb 2016 14:02:59 +0100
From: Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
To: Fu Wei <fu.wei@...aro.org>
Cc: Guenter Roeck <linux@...ck-us.net>,
Timur Tabi <timur@...eaurora.org>,
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Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>,
LKML <linux-kernel@...r.kernel.org>,
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devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
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Sudeep Holla <sudeep.holla@....com>
Subject: Re: [PATCH v10 5/5] Watchdog: ARM SBSA Generic Watchdog half
timeout panic support
Hello,
On Fri, 5 Feb 2016 17:51:52 +0800, Fu Wei wrote:
> OK, my thought is
>
> if panic is enabled :
> |--------WOR-------WS0--------WOR-------WS1
> |------timeout------(panic)------timeout-----reset
I'm quite certainly missing something completely obvious here, but how
can you get the WS1 interrupt *after* raising a panic? Aren't all
interrupts disabled and the system fully halted once you get a panic(),
especially when raised from an interrupt handler? If that's the case,
how can the system continue to do things, such as receiving the WS1
interrupt and resetting ?
Again, I'm probably missing something obvious, but I'm interested to
understand the reasoning here.
Thanks!
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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