linux-kernel - Re: [PATCH v10 5/5] Watchdog: ARM SBSA Generic Watchdog half timeout panic support

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Message-ID: <56B49EC7.4050306@codeaurora.org>
Date:	Fri, 5 Feb 2016 07:08:23 -0600
From:	Timur Tabi <timur@...eaurora.org>
To:	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
	Fu Wei <fu.wei@...aro.org>
Cc:	Guenter Roeck <linux@...ck-us.net>,
	Rob Herring <robh+dt@...nel.org>,
	Paweł Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Wim Van Sebroeck <wim@...ana.be>,
	Jon Corbet <corbet@....net>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will.deacon@....com>,
	Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>,
	LKML <linux-kernel@...r.kernel.org>,
	linux-watchdog@...r.kernel.org, linux-doc@...r.kernel.org,
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	Linaro ACPI Mailman List <linaro-acpi@...ts.linaro.org>,
	rruigrok@...eaurora.org, "Abdulhamid, Harb" <harba@...eaurora.org>,
	Christopher Covington <cov@...eaurora.org>,
	Dave Young <dyoung@...hat.com>,
	Pratyush Anand <panand@...hat.com>,
	G Gregory <graeme.gregory@...aro.org>,
	Al Stone <al.stone@...aro.org>,
	Hanjun Guo <hanjun.guo@...aro.org>,
	Jon Masters <jcm@...hat.com>, Arnd Bergmann <arnd@...db.de>,
	Leo Duran <leo.duran@....com>,
	Sudeep Holla <sudeep.holla@....com>
Subject: Re: [PATCH v10 5/5] Watchdog: ARM SBSA Generic Watchdog half timeout
 panic support

Thomas Petazzoni wrote:
>> if panic is enabled :
>> >|--------WOR-------WS0--------WOR-------WS1
>> >|------timeout------(panic)------timeout-----reset

> I'm quite certainly missing something completely obvious here, but how
> can you get the WS1 interrupt*after*  raising a panic? Aren't all
> interrupts disabled and the system fully halted once you get a panic(),
> especially when raised from an interrupt handler? If that's the case,
> how can the system continue to do things, such as receiving the WS1
> interrupt and resetting ?

Typically, WS1 is not an interrupt.  Instead, it's a hard system-level 
reset.

The hardware is capable of generating an interrupt for both WS0 and WS1. 
  However, the ACPI table only contains one interrupt value, and it's 
not clear whether that's supposed to be the WS0 interrupt or the WS1 
interrupts.

So this whole thing does assume a specfic watchdog configuration.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
Code Aurora Forum, hosted by The Linux Foundation.