linux-kernel - Re: [PATCH v10 5/5] Watchdog: ARM SBSA Generic Watchdog half timeout panic support

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Message-ID: <20160205143318.2de2815c@free-electrons.com>
Date:	Fri, 5 Feb 2016 14:33:18 +0100
From:	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
To:	Timur Tabi <timur@...eaurora.org>
Cc:	Fu Wei <fu.wei@...aro.org>, Guenter Roeck <linux@...ck-us.net>,
	Rob Herring <robh+dt@...nel.org>,
	Paweł Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Wim Van Sebroeck <wim@...ana.be>,
	Jon Corbet <corbet@....net>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will.deacon@....com>,
	Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>,
	LKML <linux-kernel@...r.kernel.org>,
	linux-watchdog@...r.kernel.org, linux-doc@...r.kernel.org,
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	Linaro ACPI Mailman List <linaro-acpi@...ts.linaro.org>,
	rruigrok@...eaurora.org, "Abdulhamid, Harb" <harba@...eaurora.org>,
	Christopher Covington <cov@...eaurora.org>,
	Dave Young <dyoung@...hat.com>,
	Pratyush Anand <panand@...hat.com>,
	G Gregory <graeme.gregory@...aro.org>,
	Al Stone <al.stone@...aro.org>,
	Hanjun Guo <hanjun.guo@...aro.org>,
	Jon Masters <jcm@...hat.com>, Arnd Bergmann <arnd@...db.de>,
	Leo Duran <leo.duran@....com>,
	Sudeep Holla <sudeep.holla@....com>
Subject: Re: [PATCH v10 5/5] Watchdog: ARM SBSA Generic Watchdog half
 timeout panic support

Hello,

On Fri, 5 Feb 2016 07:08:23 -0600, Timur Tabi wrote:

> > I'm quite certainly missing something completely obvious here, but how
> > can you get the WS1 interrupt*after*  raising a panic? Aren't all
> > interrupts disabled and the system fully halted once you get a panic(),
> > especially when raised from an interrupt handler? If that's the case,
> > how can the system continue to do things, such as receiving the WS1
> > interrupt and resetting ?
> 
> Typically, WS1 is not an interrupt.  Instead, it's a hard system-level 
> reset.

Ah, right, true. I missed that aspect because on my HW, triggering a
system-level reset on WS1 is optional. I can actually get an interrupt
on both WS0 and WS1, and no reset at all.

But a normal configuration indeed involves having the WS1 event
configured in HW to be a system-level reset.

So, OK, it makes sense. Thanks for the clarification!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com