[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <56B8C6C7.9060105@synopsys.com>
Date: Mon, 8 Feb 2016 16:48:07 +0000
From: Joao Pinto <Joao.Pinto@...opsys.com>
To: Arnd Bergmann <arnd@...db.de>, Joao Pinto <Joao.Pinto@...opsys.com>
CC: Bjorn Helgaas <helgaas@...nel.org>, <linux-pci@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <CARLOS.PALMINHA@...opsys.com>
Subject: Re: [PATCH] link up validation moved to pcie-designware
Our
On 2/8/2016 4:46 PM, Arnd Bergmann wrote:
> On Monday 08 February 2016 16:43:33 Joao Pinto wrote:
>> Hi,
>> Ok, so what should be the retries and waiting time in your opinion?
>> The most typical is:
>>
>> retries: 10
>> delay: 100ms (usleep_range (90000, 100000))
>>
>> These values should be ok?
>>
>> I am already testing a full pcie-designware platform driver.
>>
>>
> You are the one with the datasheet, not me. ;-)
Our reference driver follows the 10x with 100ms delay between retries, so lets
follow that value. Agree?
>
> Arnd
>
Joao
Powered by blists - more mailing lists