linux-kernel - Re: [tip:x86/mm] x86/mm: Add INVPCID helpers

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Date:	Wed, 10 Feb 2016 13:08:27 +0100
From:	Borislav Petkov <bp@...en8.de>
To:	mingo@...nel.org, luto@...capital.net
Cc:	tglx@...utronix.de, oleg@...hat.com, brgerst@...il.com,
	mcgrof@...e.com, dave.hansen@...ux.intel.com,
	akpm@...ux-foundation.org, dvlasenk@...hat.com,
	peterz@...radead.org, torvalds@...ux-foundation.org,
	linux-kernel@...r.kernel.org, toshi.kani@...com, luto@...nel.org,
	aryabinin@...tuozzo.com, hpa@...or.com,
	Michael Matz <matz@...e.de>, linux-tip-commits@...r.kernel.org
Subject: Re: [tip:x86/mm] x86/mm: Add INVPCID helpers

On Tue, Feb 09, 2016 at 08:07:31AM -0800, tip-bot for Andy Lutomirski wrote:
> Commit-ID:  060a402a1ddb551455ee410de2eadd3349f2801b
> Gitweb:     http://git.kernel.org/tip/060a402a1ddb551455ee410de2eadd3349f2801b
> Author:     Andy Lutomirski <luto@...nel.org>
> AuthorDate: Fri, 29 Jan 2016 11:42:57 -0800
> Committer:  Ingo Molnar <mingo@...nel.org>
> CommitDate: Tue, 9 Feb 2016 13:36:10 +0100
> 
> x86/mm: Add INVPCID helpers
> 
> This adds helpers for each of the four currently-specified INVPCID
> modes.

...

> +static inline void __invpcid(unsigned long pcid, unsigned long addr,
> +			     unsigned long type)
> +{
> +	u64 desc[2] = { pcid, addr };
> +
> +	/*
> +	 * The memory clobber is because the whole point is to invalidate
> +	 * stale TLB entries and, especially if we're flushing global
> +	 * mappings, we don't want the compiler to reorder any subsequent
> +	 * memory accesses before the TLB flush.
> +	 *
> +	 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
> +	 * invpcid (%rcx), %rax in long mode.
> +	 */
> +	asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
> +		      : : "m" (desc), "a" (type), "c" (desc) : "memory");


---
From: Borislav Petkov <bp@...e.de>
Date: Wed, 10 Feb 2016 12:53:48 +0100
Subject: [PATCH] x86/mm: Fix INVPCID asm constraint
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

So we want to specify the dependency on both @pcid and @addr so that the
compiler doesn't reorder accesses to them *before* the TLB flush. But
for that to work, we need to express this properly in the inline asm and
deref the whole desc array, not the pointer to it. See clwb() for an
example.

This fixes the build error on 32-bit:

  arch/x86/include/asm/tlbflush.h: In function ‘__invpcid’:
  arch/x86/include/asm/tlbflush.h:26:18: error: memory input 0 is not directly addressable

which gcc4.7 caught but 5.x didn't. Which is strange. :-\

Signed-off-by: Borislav Petkov <bp@...e.de>
Cc: Andrew Morton <akpm@...ux-foundation.org>
Cc: Andrey Ryabinin <aryabinin@...tuozzo.com>
Cc: Andy Lutomirski <luto@...capital.net>
Cc: Borislav Petkov <bp@...en8.de>
Cc: Brian Gerst <brgerst@...il.com>
Cc: Dave Hansen <dave.hansen@...ux.intel.com>
Cc: Denys Vlasenko <dvlasenk@...hat.com>
Cc: H. Peter Anvin <hpa@...or.com>
Cc: Ingo Molnar <mingo@...nel.org>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Luis R. Rodriguez <mcgrof@...e.com>
Cc: Michael Matz <matz@...e.de>
Cc: Oleg Nesterov <oleg@...hat.com>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Toshi Kani <toshi.kani@...com>
Cc: linux-mm@...ck.org
---
 arch/x86/include/asm/tlbflush.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index 6f9e27aa2aaf..c820b2a9e026 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -23,7 +23,7 @@ static inline void __invpcid(unsigned long pcid, unsigned long addr,
 	 * invpcid (%rcx), %rax in long mode.
 	 */
 	asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
-		      : : "m" (desc), "a" (type), "c" (desc) : "memory");
+		      : : "m" (*desc), "a" (type), "c" (desc) : "memory");
 }
 
 #define INVPCID_TYPE_INDIV_ADDR		0
-- 
2.3.5


-- 
Regards/Gruss,
    Boris.

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