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Message-ID: <20160211112758.GA5565@pd.tnic>
Date: Thu, 11 Feb 2016 12:27:58 +0100
From: Borislav Petkov <bp@...en8.de>
To: tthayer@...nsource.altera.com
Cc: dougthompson@...ssion.com, m.chehab@...sung.com,
robh+dt@...nel.org, pawel.moll@....com, mark.rutland@....com,
ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
linux@....linux.org.uk, dinguyen@...nsource.altera.com,
grant.likely@...aro.org, devicetree@...r.kernel.org,
linux-doc@...r.kernel.org, linux-edac@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
tthayer.linux@...il.com
Subject: Re: [PATCHv10 2/4] ARM: dts: Add Altera L2 Cache and OCRAM EDAC
entries
On Wed, Feb 10, 2016 at 01:26:22PM -0600, tthayer@...nsource.altera.com wrote:
> From: Thor Thayer <tthayer@...nsource.altera.com>
>
> Adding the device tree entries and bindings needed to support
> the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
> an earlier patch to declare and setup On-chip RAM properly.
> http://www.spinics.net/lists/devicetree/msg51117.html
For the future, please use git commit IDs and not some, probably
unstable URLs:
8b907c8b62ac ("arm: dts: socfpga: Add OCRAM node")
I've fixed it now while applying.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
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