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Date: Thu, 18 Feb 2016 14:13:01 +0900 From: Krzysztof Kozlowski <k.kozlowski@...sung.com> To: Kukjin Kim <kgene@...nel.org>, Krzysztof Kozlowski <k.kozlowski@...sung.com>, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org Cc: Lukasz Majewski <l.majewski@...sung.com>, Zhang Rui <rui.zhang@...el.com>, Eduardo Valentin <edubezval@...il.com>, Viresh Kumar <viresh.kumar@...aro.org> Subject: [PATCH v2 1/3] ARM: dts: Add cooling levels for CPUs on exynos5420 On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and 12 steps for big core (700-1800 MHz). Add respective cooling cells. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@...sung.com> --- Changes since v1: 1. Add cooling properties to all CPUs (suggested by Viresh). --- arch/arm/boot/dts/exynos5420-cpus.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index 261d25173f61..5c052d7ff554 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -33,6 +33,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu1: cpu@1 { @@ -42,6 +45,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu2: cpu@2 { @@ -51,6 +57,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu3: cpu@3 { @@ -60,6 +69,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu4: cpu@100 { @@ -70,6 +82,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; cpu5: cpu@101 { @@ -79,6 +94,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; cpu6: cpu@102 { @@ -88,6 +106,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; cpu7: cpu@103 { @@ -97,6 +118,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; }; }; -- 2.5.0
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