linux-kernel - Re: [PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit

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Message-ID: <20160218173428.GE16883@arm.com>
Date:	Thu, 18 Feb 2016 17:34:28 +0000
From:	Will Deacon <will.deacon@....com>
To:	Jan Glauber <jglauber@...ium.com>
Cc:	Mark Rutland <mark.rutland@....com>, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit

On Thu, Feb 18, 2016 at 05:50:13PM +0100, Jan Glauber wrote:
> With the long cycle counter bit (LC) disabled the cycle counter is not
> working on ThunderX SOC (ThunderX only implements Aarch64).
> Also, according to documentation LC == 0 is deprecated.
> 
> To keep the code simple the patch does not introduce 64 bit wide counter
> functions. Instead writing the cycle counter always sets the upper
> 32 bits so overflow interrupts are generated as before.
> 
> Original patch from Andrew Pinksi <Andrew.Pinksi@...iumnetworks.com>

What does this mean? Do we need Andrew's S-o-B, or is this a fresh patch?

Will