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Message-ID: <alpine.DEB.2.02.1603050030190.9477@linux-builds1>
Date: Sat, 5 Mar 2016 00:36:16 -0600
From: Dinh Nguyen <dinguyen@...nsource.altera.com>
To: <tthayer@...nsource.altera.com>
CC: <bp@...en8.de>, <dougthompson@...ssion.com>,
<m.chehab@...sung.com>, <robh+dt@...nel.org>, <pawel.moll@....com>,
<mark.rutland@....com>, <ijc+devicetree@...lion.org.uk>,
<galak@...eaurora.org>, <linux@....linux.org.uk>,
<grant.likely@...aro.org>, <devicetree@...r.kernel.org>,
<linux-doc@...r.kernel.org>, <linux-edac@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <tthayer.linux@...il.com>
Subject: Re: [PATCH 4/5] ARM: socfpga: Enable Arria10 L2 cache ECC on
startup
On Tue, 1 Mar 2016, tthayer@...nsource.altera.com wrote:
> From: Thor Thayer <tthayer@...nsource.altera.com>
>
> Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be
> enabled before data is stored in memory otherwise the ECC will fail
> on reads.
>
> Signed-off-by: Thor Thayer <tthayer@...nsource.altera.com>
> ---
> arch/arm/mach-socfpga/l2_cache.c | 42 ++++++++++++++++++++++++++++++++++----
> 1 file changed, 38 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/l2_cache.c b/arch/arm/mach-socfpga/l2_cache.c
> index e3907ab..b197218 100644
> --- a/arch/arm/mach-socfpga/l2_cache.c
> +++ b/arch/arm/mach-socfpga/l2_cache.c
> @@ -17,14 +17,31 @@
> #include <linux/of_platform.h>
> #include <linux/of_address.h>
>
> +#include "core.h"
> +
> +/* A10 System Manager ECC interrupt mask control registers */
> +#define A10_L2_ECC_CTRL_OFST 0x0
> +
> +#define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
> +#define A10_L2_ECC_INT_CLR_OFST 0xA8
> +
> +#define A10_MPU_CTRL_L2_ECC_EN BIT(0)
> +#define A10_ECC_INTMASK_CLR_EN BIT(0)
> +#define A10_ECC_INT_CLR (BIT(31) | BIT(15))
> +
> void socfpga_init_l2_ecc(void)
> {
> struct device_node *np;
> void __iomem *mapped_l2_edac_addr;
> + const char *compat = "altr,socfpga-l2-ecc";
>
> - np = of_find_compatible_node(NULL, NULL, "altr,socfpga-l2-ecc");
> + if (of_machine_is_compatible("altr,socfpga-arria10"))
> + compat = "altr,socfpga-a10-l2-ecc";
The ARM maintainers have made comment to me about about trying to not sprinkle
these of_machine_is_compatible() all over the place. You should make the
decision during the initial probe of the machine. Please look at how the
.restart is differentiate between the 2 platforms.
> +
> + /* Find the L2 EDAC device tree node */
> + np = of_find_compatible_node(NULL, NULL, compat);
> if (!np) {
> - pr_err("Unable to find socfpga-l2-ecc in dtb\n");
> + pr_err("Unable to find %s in dtb\n", compat);
> return;
> }
>
> @@ -35,7 +52,24 @@ void socfpga_init_l2_ecc(void)
> return;
> }
>
> - /* Enable ECC */
> - writel(0x01, mapped_l2_edac_addr);
> + if (of_machine_is_compatible("altr,socfpga-arria10")) {
Same comment as above here.
BR,
Dinh
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