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Message-Id: <1457576219-7971-5-git-send-email-stefan@agner.ch>
Date: Wed, 9 Mar 2016 18:16:45 -0800
From: Stefan Agner <stefan@...er.ch>
To: shawnguo@...nel.org, mturquette@...libre.com, sboyd@...eaurora.org
Cc: kernel@...gutronix.de, sergeimir@...raft.com, tglx@...utronix.de,
jason@...edaemon.net, marc.zyngier@....com, robh+dt@...nel.org,
pawel.moll@....com, mark.rutland@....com,
ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
Stefan Agner <stefan@...er.ch>
Subject: [PATCH 04/18] ARM: dts: vf610: add on-chip SRAM
Add Vybrids massive on-chip SRAM areas. Make use of the memory
region functionality to denominate the retained SRAM area in
LPSTOP2 and LPSTOP3.
Signed-off-by: Stefan Agner <stefan@...er.ch>
---
arch/arm/boot/dts/vfxxx.dtsi | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 909988d..b038ea4 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -91,6 +91,43 @@
interrupt-parent = <&gpc>;
ranges;
+ ocram0: sram@...00000 {
+ compatible = "mmio-sram";
+ reg = <0x3f000000 0x40000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x3f000000 0x40000>;
+
+ stbyram1@0 {
+ reg = <0x0 0x4000>;
+ label = "stbyram1";
+ pool;
+ };
+
+ stbyram2@...0 {
+ reg = <0x4000 0xc000>;
+ label = "stbyram2";
+ pool;
+ };
+ };
+
+ ocram1: sram@...40000 {
+ compatible = "mmio-sram";
+ reg = <0x3f040000 0x40000>;
+ };
+
+ gfxram0: sram@...00000 {
+ compatible = "mmio-sram";
+ reg = <0x3f400000 0x80000>;
+ };
+
+ /* used by L2 cache */
+ gfxram1: sram@...80000 {
+ compatible = "mmio-sram";
+ reg = <0x3f480000 0x80000>;
+ };
+
aips0: aips-bus@...00000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
--
2.7.2
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