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Message-ID: <56E247B8.4060306@rock-chips.com>
Date: Fri, 11 Mar 2016 12:21:12 +0800
From: Caesar Wang <wxt@...k-chips.com>
To: Heiko Stuebner <heiko@...ech.de>
CC: Caesar Wang <wxt@...k-chips.com>,
Jassi Brar <jassisinghbrar@...il.com>,
Mark Rutland <mark.rutland@....com>,
devicetree@...r.kernel.org,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Pawel Moll <pawel.moll@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
frank.wang@...k-chips.com,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
linux-kernel@...r.kernel.org, linux-rockchip@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>,
Kumar Gala <galak@...eaurora.org>,
Olof Johansson <olof@...om.net>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v1 3/3] ARM64: dts: rk3368: Add mailbox device nodes
于 2015年10月27日 15:31, Caesar Wang 写道:
> This adds mailbox device nodes in dts.
>
> Mailbox is used by the Rockchip CPU cores to communicate
> requests to MCU processor.
>
> Signed-off-by: Caesar Wang <wxt@...k-chips.com>
> ---
>
> Changes in v1:
> - PATCH[3/3] dts:
> - fix "processormZ"--> "processor",the miss-fingerboard.
> - Remove the shared memory in mailbox controller dtsi.
>
> arch/arm64/boot/dts/rockchip/rk3368.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> index cc093a4..cefdad3 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> @@ -484,6 +484,18 @@
> status = "disabled";
> };
>
> + mbox: mbox@...b0000 {
> + compatible = "rockchip,rk3368-mailbox";
> + reg = <0x0 0xff6b0000 0x0 0x1000>,
s/,/;
> + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_MAILBOX>;
> + clock-names = "pclk_mailbox";
> + #mbox-cells = <1>;
> + };
> +
> pmugrf: syscon@...38000 {
> compatible = "rockchip,rk3368-pmugrf", "syscon";
> reg = <0x0 0xff738000 0x0 0x1000>;
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