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Message-Id: <1458770712-10880-18-git-send-email-mmcclint@codeaurora.org>
Date: Wed, 23 Mar 2016 17:05:12 -0500
From: Matthew McClintock <mmcclint@...eaurora.org>
To: andy.gross@...aro.org, linux-arm-msm@...r.kernel.org
Cc: qca-upstream.external@....qualcomm.com,
Matthew McClintock <mmcclint@...eaurora.org>,
David Brown <david.brown@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Russell King <linux@....linux.org.uk>,
linux-soc@...r.kernel.org (open list:ARM/QUALCOMM SUPPORT),
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
DEVICE TREE BINDINGS),
linux-arm-kernel@...ts.infradead.org (moderated list:ARM PORT),
linux-kernel@...r.kernel.org (open list)
Subject: [PATCH 17/17] qcom: ipq4019: add DMA nodes to ipq4019 SoC and DK01 device tree
This adds the blsp_dma node to the device tree and the required
properties for using DMA with serial
Signed-off-by: Matthew McClintock <mmcclint@...eaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 4 ++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 15 +++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 2c347ad..b9457dd2 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -72,6 +72,10 @@
};
};
+ blsp_dma: dma@...4000 {
+ status = "ok";
+ };
+
spi_0: spi@...5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 3cd42c0..5c08d19 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -123,6 +123,17 @@
interrupts = <0 208 0>;
};
+ blsp_dma: dma@...4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07884000 0x23000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
spi_0: spi@...5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
@@ -224,6 +235,8 @@
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp_dma 1>, <&blsp_dma 0>;
+ dma-names = "rx", "tx";
};
serial@...0000 {
@@ -234,6 +247,8 @@
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp_dma 3>, <&blsp_dma 2>;
+ dma-names = "rx", "tx";
};
watchdog@...7000 {
--
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