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Message-ID: <1460554120.6620.137.camel@linux.intel.com>
Date: Wed, 13 Apr 2016 16:28:40 +0300
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Fei Yang <fei.yang@...ux.intel.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
Boon Leong Ong <boon.leong.ong@...el.com>
Cc: linux-kernel@...r.kernel.org, Fei Yang <fei.yang@...el.com>,
"Syrjala, Ville" <ville.syrjala@...el.com>
Subject: Re: [PATCH] IOSF: Add interface for the cases requiring fid
On Fri, 2016-04-08 at 14:02 -0700, Fei Yang wrote:
> From: Fei Yang <fei.yang@...el.com>
>
> Some implementations may require an additional step for setting the
> FID
> bits to ensure correct transactions over the IOSF side band interface.
> Add the FID support accordingly for such implementations
>
Cc'ed to Ville to take a look.
As mentioned in a follow up the user of this is "a DRM based display
controller driver, which is not currently in the upstream.
But this API is a prerequisite of pushing the display driver upstream."
> Change-Id: Ic0227f9e74133a3203aa08e8471939f905d19622
> Signed-off-by: Fei Yang <fei.yang@...el.com>
> ---
> arch/x86/include/asm/iosf_mbi.h | 27 ++++++++++++++
> arch/x86/platform/intel/iosf_mbi.c | 73
> ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 100 insertions(+)
>
> diff --git a/arch/x86/include/asm/iosf_mbi.h
> b/arch/x86/include/asm/iosf_mbi.h
> index b41ee16..71511ba 100644
> --- a/arch/x86/include/asm/iosf_mbi.h
> +++ b/arch/x86/include/asm/iosf_mbi.h
> @@ -8,6 +8,7 @@
> #define MBI_MCR_OFFSET 0xD0
> #define MBI_MDR_OFFSET 0xD4
> #define MBI_MCRX_OFFSET 0xD8
> +#define MBI_MCRP_OFFSET 0xDC
>
> #define MBI_RD_MASK 0xFEFFFFFF
> #define MBI_WR_MASK 0X01000000
> @@ -88,6 +89,32 @@ int iosf_mbi_write(u8 port, u8 opcode, u32 offset,
> u32 mdr);
> */
> int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32
> mask);
>
> +/**
> + * iosf_mbi_read_with_fid() - MailBox Interface read command
> requiring fid
> + * @fid: fid bits
> + * @port: port indicating subunit being accessed
> + * @opcode: port specific read or write opcode
> + * @offset: register address offset
> + * @mdr: register data to be read
> + *
> + * Locking is handled by spinlock - cannot sleep.
> + * Return: Nonzero on error
> + */
> +int iosf_mbi_read_with_fid(u32 fid, u8 port, u8 opcode, u32 offset,
> u32 *mdr);
> +
> +/**
> + * iosf_mbi_write_with_fid() - MailBox unmasked write command
> requiring fid
> + * @fid: fid bits
> + * @port: port indicating subunit being accessed
> + * @opcode: port specific read or write opcode
> + * @offset: register address offset
> + * @mdr: register data to be written
> + *
> + * Locking is handled by spinlock - cannot sleep.
> + * Return: Nonzero on error
> + */
> +int iosf_mbi_write_with_fid(u32 fid, u8 port, u8 opcode, u32 offset,
> u32 mdr);
> +
> #else /* CONFIG_IOSF_MBI is not enabled */
> static inline
> bool iosf_mbi_available(void)
> diff --git a/arch/x86/platform/intel/iosf_mbi.c
> b/arch/x86/platform/intel/iosf_mbi.c
> index edf2c54..af182c1 100644
> --- a/arch/x86/platform/intel/iosf_mbi.c
> +++ b/arch/x86/platform/intel/iosf_mbi.c
> @@ -98,6 +98,24 @@ fail_write:
> return result;
> }
>
> +static int iosf_mbi_pci_write_fid(u32 fid)
> +{
> + int result;
> +
> + if (!mbi_pdev)
> + return -ENODEV;
> +
> + result = pci_write_config_dword(mbi_pdev, MBI_MCRP_OFFSET,
> fid);
> + if (result < 0)
> + goto fail_fid_write;
> +
> + return 0;
> +
> +fail_fid_write:
> + dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n",
> result);
> + return result;
> +}
> +
> int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
> {
> u32 mcr, mcrx;
> @@ -183,6 +201,61 @@ int iosf_mbi_modify(u8 port, u8 opcode, u32
> offset, u32 mdr, u32 mask)
> }
> EXPORT_SYMBOL(iosf_mbi_modify);
>
> +/*
> + * Some IP blocks require fid to access their registers.
> + * fid value is programmed through MCRP register, see above function
> + * iosf_mbi_pci_write_fid() for details.
> + */
> +int iosf_mbi_read_with_fid(u32 fid, u8 port, u8 opcode, u32 offset,
> u32 *mdr)
> +{
> + u32 mcr, mcrx;
> + unsigned long flags;
> + int ret;
> +
> + /*Access to the GFX unit is handled by GPU code */
> + if (port == BT_MBI_UNIT_GFX) {
> + WARN_ON(1);
> + return -EPERM;
> + }
> +
> + mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
> + mcrx = offset & MBI_MASK_HI;
> +
> + spin_lock_irqsave(&iosf_mbi_lock, flags);
> + ret = iosf_mbi_pci_write_fid(fid);
> + if (!ret)
> + ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr);
> + spin_unlock_irqrestore(&iosf_mbi_lock, flags);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(iosf_mbi_read_with_fid);
> +
> +int iosf_mbi_write_with_fid(u32 fid, u8 port, u8 opcode, u32 offset,
> u32 mdr)
> +{
> + u32 mcr, mcrx;
> + unsigned long flags;
> + int ret;
> +
> + /*Access to the GFX unit is handled by GPU code */
> + if (port == BT_MBI_UNIT_GFX) {
> + WARN_ON(1);
> + return -EPERM;
> + }
> +
> + mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
> + mcrx = offset & MBI_MASK_HI;
> +
> + spin_lock_irqsave(&iosf_mbi_lock, flags);
> + ret = iosf_mbi_pci_write_fid(fid);
> + if (!ret)
> + ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr);
> + spin_unlock_irqrestore(&iosf_mbi_lock, flags);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(iosf_mbi_write_with_fid);
> +
> bool iosf_mbi_available(void)
> {
> /* Mbi isn't hot-pluggable. No remove routine is provided */
--
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Intel Finland Oy
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