lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <alpine.DEB.2.11.1604220954260.3941@nanos>
Date:	Fri, 22 Apr 2016 09:58:31 +0200 (CEST)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Borislav Petkov <bp@...en8.de>
cc:	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
	vince@...ter.net, eranian@...gle.com,
	Arnaldo Carvalho de Melo <acme@...radead.org>,
	Mathieu Poirier <mathieu.poirier@...aro.org>
Subject: Re: [PATCH v1 2/5] perf/x86/intel/pt: IP filtering register/cpuid
 bits

On Thu, 21 Apr 2016, Borislav Petkov wrote:

> On Thu, Apr 21, 2016 at 08:55:38PM +0200, Thomas Gleixner wrote:
> > I have to disagree here. The MSRs itself can really go into msr-index.h while
> > the bit definitions might go elsewhere. What's wrong with having all MSRs at a
> > central place?
> 
> Same reason as for pci_ids.h - to contain only MSRs which are used in
> multiple compilation units.

That's really not the same thing. pci ids are issued by a gazillion of vendors
for a bazillion of different devices. There is no consistent view for them.

MSRs on the other hand are x86 specific registers nicely defined in the
SDM/APM and having at least the MSR defines in a single header makes a lot of
sense.

Thanks,

	tglx


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ