linux-kernel - Re: [PATCH v1 2/5] perf/x86/intel/pt: IP filtering register/cpuid bits

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Fri, 22 Apr 2016 11:34:00 +0200
From:	Borislav Petkov <bp@...en8.de>
To:	Thomas Gleixner <tglx@...utronix.de>
Cc:	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
	vince@...ter.net, eranian@...gle.com,
	Arnaldo Carvalho de Melo <acme@...radead.org>,
	Mathieu Poirier <mathieu.poirier@...aro.org>
Subject: Re: [PATCH v1 2/5] perf/x86/intel/pt: IP filtering register/cpuid
 bits

On Fri, Apr 22, 2016 at 09:58:31AM +0200, Thomas Gleixner wrote:
> That's really not the same thing. pci ids are issued by a gazillion of vendors
> for a bazillion of different devices. There is no consistent view for them.

So my reasoning was to not add *every* MSR to that file, especially the
ones which are strictly topical. For example, the MCA MSRs which can
easily live in mce.h as nothing else needs to touch them...

> MSRs on the other hand are x86 specific registers nicely defined in the
> SDM/APM and having at least the MSR defines in a single header makes a lot of
> sense.

... but ok. I see there could be some merit of keeping them all in the
same place. We can always change that if the handling of msr-index.h
starts becoming too unwieldy.

In any case, we'd need to zap

053080a9d1c8 ("x86/msr: Document msr-index.h rule for addition")

now.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.