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Message-ID: <20160426190009.GC8162@amd>
Date: Tue, 26 Apr 2016 21:00:10 +0200
From: Pavel Machek <pavel@....cz>
To: Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>
Cc: gregkh@...uxfoundation.org, Andy Lutomirski <luto@...nel.org>,
Borislav Petkov <bp@...e.de>,
Boris Ostrovsky <boris.ostrovsky@...cle.com>,
"open list:STAGING SUBSYSTEM" <devel@...verdev.osuosl.org>,
Ingo Molnar <mingo@...nel.org>,
Kristen Carlson Accardi <kristen@...ux.intel.com>,
"open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>,
Mathias Krause <minipli@...glemail.com>,
Thomas Gleixner <tglx@...utronix.de>,
Wan Zongshun <Vincent.Wan@....com>
Subject: Re: [PATCH 0/6] Intel Secure Guard Extensions
On Mon 2016-04-25 20:34:07, Jarkko Sakkinen wrote:
> Intel(R) SGX is a set of CPU instructions that can be used by
> applications to set aside private regions of code and data. The code
> outside the enclave is disallowed to access the memory inside the
> enclave by the CPU access control.
>
> The firmware uses PRMRR registers to reserve an area of physical memory
> called Enclave Page Cache (EPC). There is a hardware unit in the
> processor called Memory Encryption Engine. The MEE encrypts and decrypts
> the EPC pages as they enter and leave the processor package.
What are non-evil use cases for this?
Pavel
--
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