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Message-ID: <CACRpkdZ8NsXCaRgVCVKKiuGoCEWvAUx81Do5XangEq3Fptj3ZA@mail.gmail.com>
Date:	Fri, 29 Apr 2016 09:42:55 +0200
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Patrice CHOTARD <patrice.chotard@...com>
Cc:	Lee Jones <lee.jones@...aro.org>,
	Alexandre Courbot <gnurou@...il.com>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Maxime Coquelin <maxime.coquelin@...com>,
	amelie.delaunay@...com, Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <kernel@...gutronix.de>,
	Dinh Nguyen <dinguyen@...nsource.altera.com>,
	Viresh Kumar <vireshk@...nel.org>,
	Shiraz Hashim <shiraz.linux.kernel@...il.com>,
	Thierry Reding <thierry.reding@...il.com>,
	Marcel Ziswiler <marcel.ziswiler@...adex.com>,
	Stefan Agner <stefan@...er.ch>, dev@...xeye.de
Subject: Re: [PATCH v2 07/10] gpio: stmpe: rework registers access

On Thu, Apr 28, 2016 at 2:13 PM,  <patrice.chotard@...com> wrote:

> From: Patrice Chotard <patrice.chotard@...com>
>
> This update allows to use registers map as following :
> regs[reg_index + offset] instead of
> regs[reg_index] + offset
>
> This makes code clearer and will facilitate the addition of STMPE1600
> on which LSB and MSB registers are respectively located at addr and addr + 1.
> Despite for all others STMPE variant, LSB and MSB registers are respectively
> located in reverse order at addr + 1 and addr.
>
> For variant which have 3 registers's bank, we use LSB,CSB and MSB indexes
> which contains respectively LSB (or LOW), CSB (or MID) and MSB (or HIGH)
> register addresses (STMPE1801/STMPE24xx).
> For variant which have 2 registers's bank, we use LSB and CSB indexes only.
> In this case the CSB index contains the MSB regs address (STMPE 1601).
>
> Signed-off-by: Patrice Chotard <patrice.chotard@...com>

Reviewed-by: Linus Walleij <linus.walleij@...aro.org>

Yours,
Linus Walleij

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