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Message-ID: <CAAMH-yumeh+MUADCk7wbeSO-hdVLT82jmkn2swYmuD8HndrKFA@mail.gmail.com> Date: Fri, 29 Apr 2016 14:52:34 +0200 From: Gary Bisson <gary.bisson@...ndarydevices.com> To: Fabio Estevam <festevam@...il.com> Cc: Andrey Smirnov <andrew.smirnov@...il.com>, "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, Richard Zhu <Richard.Zhu@...escale.com>, linux-kernel <linux-kernel@...r.kernel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, Lucas Stach <l.stach@...gutronix.de> Subject: Re: [PATCH v3 2/3] PCI: imx6: Implement reset sequence for i.MX6+ Hi all, On Fri, Apr 29, 2016 at 3:47 AM, Fabio Estevam <festevam@...il.com> wrote: > On Wed, Apr 20, 2016 at 12:45 PM, Andrey Smirnov > <andrew.smirnov@...il.com> wrote: >> I.MX6+ has a dedicated bit for reseting PCIe core, which should be used >> instead of a regular reset sequence since using the latter will hang the >> SoC. >> >> This commit is based on c34068d48273e24d392d9a49a38be807954420ed from >> http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git >> >> Signed-off-by: Andrey Smirnov <andrew.smirnov@...il.com> > > Reviewed-by: Fabio Estevam <fabio.estevam@....com> Tested on a Nitrogen6QP_MAX with an Intel WiFi Link 5300 PCIe card. Everything is working properly (Gen1 speed). # lspci 00:00.0 Class 0604: 16c3:abcd 01:00.0 Class 0280: 8086:4235 Tested-by: Gary Bisson <gary.bisson@...ndarydevices.com> Thanks, Gary
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