lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <1463449293.16584.127.camel@buserror.net>
Date:	Mon, 16 May 2016 20:41:33 -0500
From:	Scott Wood <oss@...error.net>
To:	Qiang Zhao <qiang.zhao@....com>
Cc:	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Xiaobo Xie <xiaobo.xie@....com>,
	Yang-Leo Li <leoyang.li@....com>,
	"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>
Subject: Re: [v5,1/7] QE: Add IC, SI and SIRAM document to device tree
 bindings.

On Tue, 2016-05-17 at 01:18 +0000, Qiang Zhao wrote:
> On Tue, May 17, 2016 at 07:22AM, Scott Wood wrote:
> > -----Original Message-----
> > From: Scott Wood [mailto:oss@...error.net]
> > Sent: Tuesday, May 17, 2016 7:22 AM
> > To: Qiang Zhao <qiang.zhao@....com>
> > Cc: robh+dt@...nel.org; devicetree@...r.kernel.org; linux-
> > kernel@...r.kernel.org; Xiaobo Xie <xiaobo.xie@....com>; Yang-Leo Li
> > <leoyang.li@....com>; linuxppc-dev@...ts.ozlabs.org
> > Subject: Re: [v5,1/7] QE: Add IC, SI and SIRAM document to device tree
> > bindings.
> > 
> > On Wed, Mar 09, 2016 at 09:21:28AM +0800, Zhao Qiang wrote:
> > > Add IC, SI and SIRAM document of QE to
> > > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> > > 
> > > Signed-off-by: Zhao Qiang <qiang.zhao@....com>
> > > Acked-by: Rob Herring <robh@...nel.org>
> > > ---
> > > changes for v2
> > > 	- Add interrupt-controller in Required properties
> > > 	- delete address-cells and size-cells for qe-si and qe-siram Changes
> > > for v3
> > > 	- Add SoC specific caompatible strings to qe-si and qe-siram Changes
> > > for v4
> > > 	- NA
> > > Changes for v5
> > > 	- NA
> > > 
> > >  .../devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt  | 50
> > > ++++++++++++++++++++++
> > >  1 file changed, 50 insertions(+)
> > > +* Serial Interface Block (SI)
> > > +
> > > +The SI manages the routing of eight TDM lines to the QE block serial
> > > +drivers , the MCC and the UCCs, for receive and transmit.
> > > +
> > > +Required properties:
> > > +- compatible : should be "fsl,t1040-qe-si".
> > > +- reg : Address range of SI register set.
> > 
> > Is t1040 the only chip that has or will ever have this?
> 
> There also be t1024 and ls1043 supporting si.
> I thought to add them when adding their device node.
> If you think it is better to add them now, I will modify.

The binding is saying that the compatible "should" be "fsl,t1040-qe-si"
regardless of whether it's actually a t1040.  Instead say that compatible must
include "fsl,<chip>-qe-si" and give t1040 as an example.  If you intend
"fsl,t1040-qe-si" to be something that other compatible chips list, in
addition to their own <chip> compatibles, then also say that explicitly.

-Scott

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ