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Message-ID: <1463495466-29689-3-git-send-email-paul.burton@imgtec.com> Date: Tue, 17 May 2016 15:31:05 +0100 From: Paul Burton <paul.burton@...tec.com> To: <linux-mips@...ux-mips.org>, Ralf Baechle <ralf@...ux-mips.org> CC: Matt Redfearn <matt.redfearn@...tec.com>, Paul Burton <paul.burton@...tec.com>, Qais Yousef <qais.yousef@...tec.com>, <linux-kernel@...r.kernel.org>, Thomas Gleixner <tglx@...utronix.de>, "Markos Chandras" <markos.chandras@...tec.com> Subject: [PATCH 2/3] MIPS: smp-cps: Clear Status IPL field when using EIC When using an external interrupt controller (EIC) the interrupt mask bits in the cop0 Status register are reused for the Interrupt Priority Level, and any interrupts with a priority lower than the field will be ignored. Clear the field to 0 by default such that all interrupts are serviced. Signed-off-by: Paul Burton <paul.burton@...tec.com> --- arch/mips/kernel/smp-cps.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 253e140..f19f0d3 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -307,8 +307,12 @@ static void cps_init_secondary(void) if (cpu_has_mipsmt) dmt(); - change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | - STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); + if (cpu_has_veic) + clear_c0_status(ST0_IM); + else + change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | + STATUSF_IP4 | STATUSF_IP5 | + STATUSF_IP6 | STATUSF_IP7); } static void cps_smp_finish(void) -- 2.8.2
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