[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-id: <6479e0c0-97fb-ca3b-1337-6ed11410d94f@samsung.com>
Date: Wed, 25 May 2016 08:51:05 +0200
From: Marek Szyprowski <m.szyprowski@...sung.com>
To: Javier Martinez Canillas <javier@....samsung.com>,
linux-kernel@...r.kernel.org
Cc: devicetree@...r.kernel.org, Kukjin Kim <kgene@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Krzysztof Kozlowski <k.kozlowski@...sung.com>,
Mauro Carvalho Chehab <mchehab@....samsung.com>,
Shuah Khan <shuahkh@....samsung.com>,
Stephen Boyd <sboyd@...eaurora.org>,
linux-samsung-soc@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Tomasz Figa <tomasz.figa@...il.com>, linux-clk@...r.kernel.org,
Nicolas Dufresne <nicolas.dufresne@...labora.com>,
Andrzej Hajda <a.hajda@...sung.com>
Subject: Re: [PATCH 0/2] ARM: dts: Fix imprecise external abort error when
accessing Exynos MFC
Hello,
On 2016-05-24 19:41, Javier Martinez Canillas wrote:
> This series fixes an imprecise external abort error when accessing the
> Exynos MFC registers due the power domain configuration requiring the
> aclk333 clock to be enabled during a domain switch.
>
> There isn't a dependency between the clock and Linux Samsung SoC trees
> because the CLK_ACLK333 clock ID is already defined so the patches can
> be picked indepedently by the relevant subsystem maintainers.
Tested-by: Marek Szyprowski <m.szyprowski@...sung.com>
I'm really curious what kind of async-bridge is there, but this patch
really fixes the problem with mfc power domain.
> Best regards,
> Javier
>
>
> Javier Martinez Canillas (2):
> clk: exynos5420: Set ID for aclk333 gate clock
> ARM: dts: Add async-bridge clock to MFC power domain for Exynos5420
>
> arch/arm/boot/dts/exynos5420.dtsi | 5 +++--
> drivers/clk/samsung/clk-exynos5420.c | 2 +-
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
Powered by blists - more mailing lists