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Message-ID: <CAKfKVtE-2rYVmCK1OOzitayH7AzUQHnspoEv6RBLCxUJVnVksg@mail.gmail.com>
Date: Mon, 30 May 2016 11:47:01 +0530
From: Shubhrajyoti Datta <shubhrajyoti.datta@...il.com>
To: Kedareswara rao Appana <appana.durga.rao@...inx.com>
Cc: Rob Herring <robh+dt@...nel.org>, Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Michal Simek <michal.simek@...inx.com>,
Sören Brinkmann <soren.brinkmann@...inx.com>,
vinod.koul@...el.com, dan.j.williams@...el.com, appanad@...inx.com,
Moritz Fischer <moritz.fischer@...us.com>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
luis@...ethencourt.com, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
dmaengine@...r.kernel.org,
Punnaiah Choudary Kalluri <punnaia@...inx.com>
Subject: Re: [PATCH v9 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support
> + */
> +static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan,
> + struct zynqmp_dma_desc_sw *desc)
> +{
> + dma_addr_t addr;
> +
> + addr = desc->src_p;
> + writel(addr, chan->regs + ZYNQMP_DMA_SRC_START_LSB);
> + writel(upper_32_bits(addr), chan->regs + ZYNQMP_DMA_SRC_START_MSB);
Can we combine the two writes to a 64bit write.
It may be helpful on 64-bit systems.
> + addr = desc->dst_p;
> + writel(addr, chan->regs + ZYNQMP_DMA_DST_START_LSB);
> + writel(upper_32_bits(addr), chan->regs + ZYNQMP_DMA_DST_START_MSB);
> +}
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