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Message-ID: <CAPcyv4jWJ8X=2+GmYcoc7SUocdwYrx+5zud5JgXSD6KfOgA8dA@mail.gmail.com>
Date:	Tue, 7 Jun 2016 11:15:30 -0700
From:	Dan Williams <dan.j.williams@...el.com>
To:	"Kani, Toshimitsu" <toshi.kani@....com>
Cc:	"linux-nvdimm@...ts.01.org" <linux-nvdimm@...ts.01.org>,
	"hch@....de" <hch@....de>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"david@...morbit.com" <david@...morbit.com>
Subject: Re: [PATCH 04/13] libnvdimm, nfit: move flush hint mapping to dimm driver

On Tue, Jun 7, 2016 at 11:11 AM, Kani, Toshimitsu <toshi.kani@....com> wrote:
> On Sat, 2016-06-04 at 13:52 -0700, Dan Williams wrote:
>  :
>> diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c
>> index 420e1a5e2250..5b6f85d00bb5 100644
>> --- a/drivers/nvdimm/region_devs.c
>> +++ b/drivers/nvdimm/region_devs.c
>> @@ -803,11 +803,29 @@ EXPORT_SYMBOL_GPL(nvdimm_volatile_region_create);
>>   */
>>  void nvdimm_flush(struct nd_region *nd_region)
>>  {
>> +int i;
>> +
>>  /*
>> - * TODO: replace wmb_pmem() usage with flush hint writes where
>> - * available.
>> + * The first wmb() is needed to 'sfence' all previous writes
>> + * such that they are architecturally visible for the platform
>> + * buffer flush.  Note that we've already arranged for pmem
>> + * writes to avoid the cache via arch_memcpy_to_pmem().  The
>> + * final wmb() ensures ordering for the NVDIMM flush write.
>>   */
>> -wmb_pmem();
>> +wmb();
>> +for (i = 0; i < nd_region->ndr_mappings; i++) {
>> +struct nd_mapping *nd_mapping = &nd_region->mapping[i];
>> +struct nvdimm_drvdata *ndd = to_ndd_unlocked(nd_mapping);
>> +
>> +/*
>> + * Note, nvdimm_drvdata guaranteed to be live since we
>> + * arrange for all associated regions to be disabled
>> + * before the dimm is disabled.
>> + */
>> +if (ndd->flush_wpq[0])
>
> Hi Dan,
>
> ndd is NULL on our system since nvdimm_probe() always fails
> in nvdimm_init_nsarea(), which then calls put_ndd() and
> nvdimm_drvdata_release().
>

Ah, thanks for the report!  I'll fix this.  We should only care about
labels being present when the DIMM has aliased BLK and PMEM capacity.

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