linux-kernel - Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY

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Message-ID: <1524911.R4OXTTYFIK@diego>
Date:	Wed, 08 Jun 2016 22:40:19 +0200
From:	Heiko Stübner <heiko@...ech.de>
To:	Rob Herring <robh@...nel.org>
Cc:	Shawn Lin <shawn.lin@...k-chips.com>,
	Kishon Vijay Abraham I <kishon@...com>,
	linux-kernel@...r.kernel.org, linux-rockchip@...ts.infradead.org,
	Doug Anderson <dianders@...omium.org>,
	Wenrui Li <wenrui.li@...k-chips.com>,
	devicetree@...r.kernel.org
Subject: Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY

Am Mittwoch, 8. Juni 2016, 15:29:00 schrieb Rob Herring:
> gOn Wed, Jun 08, 2016 at 03:25:08PM +0800, Shawn Lin wrote:
> > This patch adds a binding that describes the Rockchip PCIe PHY
> > found on Rockchip SoCs PCIe interface.
> > 
> > Signed-off-by: Shawn Lin <shawn.lin@...k-chips.com>
> > ---
> > 
> >  .../devicetree/bindings/phy/rockchip-pcie-phy.txt  | 22
> >  ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
> >  create mode 100644
> >  Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt> 
> > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> > b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file
> > mode 100644
> > index 0000000..ba8c406
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> > @@ -0,0 +1,22 @@
> > +Rockchip PCIE PHY
> > +-----------------------
> > +
> > +Required properties:
> > + - compatible: rockchip,rk3399-pcie-phy
> > + - #phy-cells: must be 0
> > +
> > +Example:
> > +
> > +grf: syscon@...70000 {
> > +	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	...
> > +
> > +	pcie_phy: phy@...0 {
> 
> unit-address needs a reg property or drop the unit address. I'd do the
> former if there's a register range you can describe here.

Hmm, I think I'd suggest going the other way - call the node pcie-phy .

While the General Register Files do contain some specific address ranges (like 
for the emmc phy, or some performance monitor things), the register at 0xe220 
is a shared register (GRF_SOC_CON8), containing both i2s and pcie setting 
bits.

Specifying register ranges suggests some form of exclusivity to me - which is 
just great for things like the emmc phy that has an actual range, but for a 
device being controlled from some shared register.


Heiko