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Message-ID: <CAD=FV=W-GCrmsdt2s1-Ua91Ch=r-PwgKqcc9-o8Hwg2bqMpUyA@mail.gmail.com>
Date: Thu, 9 Jun 2016 21:01:24 -0700
From: Doug Anderson <dianders@...omium.org>
To: Shawn Lin <shawn.lin@...k-chips.com>
Cc: Kishon Vijay Abraham I <kishon@...com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
Heiko Stuebner <heiko@...ech.de>,
Wenrui Li <wenrui.li@...k-chips.com>,
Rob Herring <robh+dt@...nel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH 1/2] Documentation: bindings: add dt documentation for
Rockchip PCIe PHY
Shawn,
On Wed, Jun 8, 2016 at 12:25 AM, Shawn Lin <shawn.lin@...k-chips.com> wrote:
> This patch adds a binding that describes the Rockchip PCIe PHY
> found on Rockchip SoCs PCIe interface.
>
> Signed-off-by: Shawn Lin <shawn.lin@...k-chips.com>
> ---
>
> .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> new file mode 100644
> index 0000000..ba8c406
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> @@ -0,0 +1,22 @@
> +Rockchip PCIE PHY
> +-----------------------
> +
> +Required properties:
> + - compatible: rockchip,rk3399-pcie-phy
> + - #phy-cells: must be 0
Code also requires reset and clock.
clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
resets = <&cru SRST_PCIEPHY>;
reset-names = "phy";
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