linux-kernel - Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger

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Message-ID: <20160609152347.GA9477@mephisto>
Date:	Thu, 9 Jun 2016 17:23:47 +0200
From:	Carlo Caione <carlo@...one.org>
To:	Marc Zyngier <marc.zyngier@....com>
Cc:	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Rob Herring <robh+dt@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	Dinh Nguyen <dinguyen@...nsource.altera.com>,
	Kevin Hilman <khilman@...libre.com>, Duc Dang <dhdang@....com>,
	Florian Fainelli <f.fainelli@...il.com>,
	Ray Jui <rjui@...adcom.com>,
	Scott Branden <sbranden@...adcom.com>,
	Kukjin Kim <kgene@...nel.org>,
	Krzysztof Kozlowski <k.kozlowski@...sung.com>,
	Jason Cooper <jason@...edaemon.net>,
	Andrew Lunn <andrew@...n.ch>,
	Gregory Clement <gregory.clement@...e-electrons.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
	Masahiro Yamada <yamada.masahiro@...ionext.com>,
	Michal Simek <michal.simek@...inx.com>,
	Sören Brinkmann <soren.brinkmann@...inx.com>,
	Tirumalesh Chalamarla <tchalamarla@...ium.com>,
	Jan Glauber <jglauber@...ium.com>,
	Hou Zhiqiang <B48286@...escale.com>,
	Wenbin Song <Wenbin.Song@...escale.com>,
	Yuan Yao <yao.yuan@....com>, Liu Gang <Gang.Liu@....com>,
	Mingkai Hu <Mingkai.Hu@...escale.com>,
	Rajesh Bhagat <rajesh.bhagat@...escale.com>,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	linux-amlogic@...ts.infradead.org,
	bcm-kernel-feedback-list@...adcom.com,
	linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer
 interrupt trigger

On 06/06/16 18:56, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
> 
> A number of DTs are being remarkably creative, declaring the interrupt
> to be edge triggered. A quick look at the TRM for the corresponding ARM
> CPUs clearly shows that this is wrong, and I've corrected those.
> For non-ARM designs (and in the absence of a publicly available TRM),
> I've made them active low as well, which can't be completely wrong
> as the GIC cannot disinguish between level low and level high.
> 
> The respective maintainers are of course welcome to prove me wrong.
> 
> While I was at it, I took the liberty to fix a couple of related issue,
> such as some spurious affinity bits on ThunderX, and their complete
> absence on ls1043a (both of which seem to be related to copy-pasting
> from other DTs).
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@....com>

For meson-gxbb.dtsi:

Acked-by: Carlo Caione <carlo@...lessm.com>

-- 
Carlo Caione