linux-kernel - Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger

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Message-ID: <575985C2.4050109@opensource.altera.com>
Date:	Thu, 9 Jun 2016 10:05:38 -0500
From:	Dinh Nguyen <dinguyen@...nsource.altera.com>
To:	Marc Zyngier <marc.zyngier@....com>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	"Rob Herring" <robh+dt@...nel.org>,
	Mark Rutland <mark.rutland@....com>
CC:	Carlo Caione <carlo@...one.org>,
	Kevin Hilman <khilman@...libre.com>,
	"Duc Dang" <dhdang@....com>,
	Florian Fainelli <f.fainelli@...il.com>,
	Ray Jui <rjui@...adcom.com>,
	Scott Branden <sbranden@...adcom.com>,
	Kukjin Kim <kgene@...nel.org>,
	Krzysztof Kozlowski <k.kozlowski@...sung.com>,
	"Jason Cooper" <jason@...edaemon.net>,
	Andrew Lunn <andrew@...n.ch>,
	Gregory Clement <gregory.clement@...e-electrons.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
	Masahiro Yamada <yamada.masahiro@...ionext.com>,
	Michal Simek <michal.simek@...inx.com>,
	Sören Brinkmann <soren.brinkmann@...inx.com>,
	"Tirumalesh Chalamarla" <tchalamarla@...ium.com>,
	Jan Glauber <jglauber@...ium.com>,
	"Hou Zhiqiang" <B48286@...escale.com>,
	Wenbin Song <Wenbin.Song@...escale.com>,
	Yuan Yao <yao.yuan@....com>, Liu Gang <Gang.Liu@....com>,
	Mingkai Hu <Mingkai.Hu@...escale.com>,
	Rajesh Bhagat <rajesh.bhagat@...escale.com>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>,
	<linux-amlogic@...ts.infradead.org>,
	<bcm-kernel-feedback-list@...adcom.com>,
	<linux-samsung-soc@...r.kernel.org>
Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt
 trigger

On 06/06/2016 12:56 PM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
> 
> A number of DTs are being remarkably creative, declaring the interrupt
> to be edge triggered. A quick look at the TRM for the corresponding ARM
> CPUs clearly shows that this is wrong, and I've corrected those.
> For non-ARM designs (and in the absence of a publicly available TRM),
> I've made them active low as well, which can't be completely wrong
> as the GIC cannot disinguish between level low and level high.
> 
> The respective maintainers are of course welcome to prove me wrong.
> 
> While I was at it, I took the liberty to fix a couple of related issue,
> such as some spurious affinity bits on ThunderX, and their complete
> absence on ls1043a (both of which seem to be related to copy-pasting
> from other DTs).
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@....com>
> ---
>  arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi    | 8 ++++----
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi          | 8 ++++----
>  arch/arm64/boot/dts/apm/apm-storm.dtsi               | 8 ++++----
>  arch/arm64/boot/dts/broadcom/ns2.dtsi                | 8 ++++----
>  arch/arm64/boot/dts/cavium/thunder-88xx.dtsi         | 8 ++++----
>  arch/arm64/boot/dts/exynos/exynos7.dtsi              | 8 ++++----
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi       | 8 ++++----
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 8 ++++----
>  arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----
>  arch/arm64/boot/dts/xilinx/zynqmp.dtsi               | 8 ++++----
>  10 files changed, 40 insertions(+), 40 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index 445aa67..c2b9bcb 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -255,10 +255,10 @@
>  		/* Local timer */
>  		timer {
>  			compatible = "arm,armv8-timer";
> -			interrupts = <1 13 0xf01>,
> -				     <1 14 0xf01>,
> -				     <1 11 0xf01>,
> -				     <1 10 0xf01>;
> +			interrupts = <1 13 0xf08>,
> +				     <1 14 0xf08>,
> +				     <1 11 0xf08>,
> +				     <1 10 0xf08>;

For SOCFPGA:

Acked-by: Dinh Nguyen <dinguyen@...nsource.altera.com>

Thanks,
Dinh