linux-kernel - Re: Using irq-crossbar.c

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Date:	Fri, 10 Jun 2016 17:05:02 +0100
From:	Marc Zyngier <marc.zyngier@....com>
To:	Sebastian Frias <sf84@...oste.net>,
	Thomas Gleixner <tglx@...utronix.de>
Cc:	LKML <linux-kernel@...r.kernel.org>,
	Grygorii Strashko <grygorii.strashko@...com>,
	Sricharan R <r.sricharan@...com>, Mason <slash.tmp@...e.fr>,
	Måns Rullgård <mans@...sr.com>
Subject: Re: Using irq-crossbar.c

On 10/06/16 16:37, Sebastian Frias wrote:
> Hi,
> 
> We are trying to write a driver for an interrupt controller (actually
> more of a crossbar) for an ARM-based SoC. This IRQ crossbar has 128
> inputs and 24 outputs, the outputs are connected directly to the
> GIC. The idea is that the GIC handles everything, and just request a
> mapping from an IRQ number (0...127, from a device's DT entry) into
> one of its 24 input lines.

"Just request a mapping...".

> By looking at current code (4.7-rc1) there seems to be a driver
> (drivers/irqchip/irq-crossbar.c) that provides similar
> functionality. The driver uses hierarchical irq domains (since commit
> 783d31863fb8 "irqchip: crossbar: Convert dra7 crossbar to stacked
> domains") which we believe we don't need because the only controller
> is the GIC.

So you need it, but you don't need it? The GIC may be the only interrupt
controller with which software interacts when the interrupt occurs, but
the crossbar does play a major role in *routing* the interrupt to the
right GIC pin.

> However the API used previously, register_routable_domain_ops(), was
> removed with commit a5561c3e845c "irqchip: gic: Get rid of routable
> domain".

And every day, I thank $DEITY for having delivered us from this evil.
Really. And it wasn't much of an API. It was the son of a hack, bolted
on the side of another hack. Unmaintainable, getting in the way. I had
much fun slaughtering it! ;-)

> Trying to use the driver with hierarchical domains (after
> modifications for our SoC), results on the kernel being blocked at
> some point:
> 
> [    0.041524] ThumbEE CPU extension supported.
> [    0.041589] Registering SWP/SWPB emulation handler
> [    0.052022] Freeing unused kernel memory: 12364K (c029b000 - c0eae000)
> [    0.074084] random: dbus-uuidgen urandom read with 0 bits of entropy available

Sorry, but that's not much of a log. Anything related to interrupts, maybe?

> We've put logs on the different domain_ops calls (alloc, free,
> translate) but they are not called, even if the DT is supposed to
> tell devices to take interrupts from this controller (*).

At all? Nobody is talking to the GIC?

> Do you have suggestions on what APIs should be used, further
> reading/examples and/or pointers on how debug this (logs to enable,
> things to look for, etc.)?

You could start with posting actual logs of an interrupt being
requested, as well as perform some basic tracing of the various
callbacks into the irqdomain and irqchip layers, all the way down to the
interrupt controllers (note the plural). Also, without seeing the code,
it is pretty difficult to make any meaningful comment...

> Thanks in advance.
> Best regards,
> 
> Sebastian
> 
> 
> (*):
> here's the diff on our DT:
> 
> --- tango4-common.dtsi	2016-06-10 16:23:08.244246017 +0200
> +++ tangox_irqv2-common.dtsi	2016-06-10 16:24:01.212588737 +0200
> @@ -47,7 +47,7 @@
>  
>  	soc {
>  		compatible = "simple-bus";
> -		interrupt-parent = <&irq0>;
> +		interrupt-parent = <&irq_mux>;
>  		#address-cells = <1>;
>  		#size-cells = <1>;
>  		ranges;
> @@ -75,7 +75,7 @@
>  		uart: serial@...00 {
>  			compatible = "ralink,rt2880-uart";
>  			reg = <0x10700 0x30>;
> -			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>  			clock-frequency = <7372800>;
>  			reg-shift = <2>;
>  		};
> @@ -83,10 +83,11 @@
>  		eth0: ethernet@...00 {
>  			compatible = "sigma,smp8734-ethernet";
>  			reg = <0x26000 0x800>;
> -			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&clkgen 1>;
>  		};
>  
> +#if 0
>  		intc: interrupt-controller@...00 {
>  			compatible = "sigma,smp8642-intc";
>  			reg = <0x6e000 0x400>;
> @@ -117,5 +118,16 @@
>  				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>  			};
>  		};
> +#else
> +		irq_mux: irq_mux@...00 {
> +			 compatible = "sigma,smp-irq-mux";
> +			 reg = <0x6f800 0x400>;
> +			 interrupt-controller;
> +			 interrupt-parent = <&gic>;
> +			 irqs-reserved = <2 3 4 125 126 127>;
> +		};

Where is the GIC? Where is the #interrupt-cells property? What is the
interrupt parent for the GIC itself? (and I'm tempted to add "What is
your name? What is you quest?", but that's because it is Friday and I
feel like I need a beer...).

	M.
-- 
Jazz is not dead. It just smells funny...