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Message-ID: <tnm1t4m8rh3ns.fsf@phwtpriv05.ph.intel.com>
Date: Fri, 17 Jun 2016 18:05:43 -0400
From: Ashutosh Dixit <ashutosh.dixit@...el.com>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: "Marciniszyn\, Mike" <mike.marciniszyn@...el.com>,
"Dalessandro\, Dennis" <dennis.dalessandro@...el.com>,
Doug Ledford <dledford@...hat.com>,
"Hefty\, Sean" <sean.hefty@...el.com>,
Hal Rosenstock <hal.rosenstock@...il.com>,
"linux-rdma\@vger.kernel.org" <linux-rdma@...r.kernel.org>,
"linux-kernel\@vger.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-pci\@vger.kernel.org" <linux-pci@...r.kernel.org>
Subject: Re: hfi1 use of PCI internals
On Thu, Jun 16 2016 at 04:08:17 PM, Bjorn Helgaas <helgaas@...nel.org> wrote:
>
> That's a good start, but leads to more questions. For example, it
> doesn't answer the obvious question of why the driver needs to
> enable/disable ASPM from interrupt context.
For power saving reasons we keep ASPM L1 enabled, but implement a
heuristic to "quickly" disable ASPM L1 when we notice PCIe traffic (as
measured by the interrupt rate) starting up. If interrupt activity
ceases ASPM L1 is re-enabled.
> Disabling ASPM should only require writing the device's Link Control
> register. The PCI core could probably provide an interface to do that
> in interrupt context.
>
> Enabling ASPM is not latency-critical and could probably be done from
> a work queue outside interrupt context, although conceptually there
> shouldn't be much required here either, and possibly the PCI core
> interface could be improved.
That is true, to keep latencies low we need to disable ASPM from
interrupt context, but re-enabling ASPM is not latency critical.
> It's possible the latency problem could be handled by some sort of
> quirk that overrides the acceptable latency.
Correct, this is another issue that needs to be resolved.
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