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Message-ID: <87fus8qkep.fsf@linux.intel.com>
Date: Mon, 20 Jun 2016 12:28:14 +0300
From: Felipe Balbi <balbi@...nel.org>
To: Roger Quadros <rogerq@...com>
Cc: tony@...mide.com, Joao.Pinto@...opsys.com,
sergei.shtylyov@...entembedded.com, peter.chen@...escale.com,
jun.li@...escale.com, grygorii.strashko@...com,
yoshihiro.shimoda.uh@...esas.com, nsekhar@...com,
linux-usb@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-omap@...r.kernel.org, Roger Quadros <rogerq@...com>
Subject: Re: [PATCH v7 1/4] usb: dwc3: core.h: add some register definitions
Hi,
Roger Quadros <rogerq@...com> writes:
> Add OTG and GHWPARAMS6 register definitions
>
> Signed-off-by: Roger Quadros <rogerq@...com>
> ---
> drivers/usb/dwc3/core.h | 84 ++++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 83 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 8fb6361..32bb7531 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -197,6 +197,15 @@
> #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
> #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
>
> +/* Global Status Register */
> +#define DWC3_GSTS_OTG_IP BIT(10)
> +#define DWC3_GSTS_BC_IP BIT(9)
> +#define DWC3_GSTS_ADP_IP BIT(8)
> +#define DWC3_GSTS_HOST_IP BIT(7)
> +#define DWC3_GSTS_DEVICE_IP BIT(6)
> +#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
> +#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
> +
> /* Global USB2 PHY Configuration Register */
> #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
> #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
> @@ -269,7 +278,12 @@
> #define DWC3_MAX_HIBER_SCRATCHBUFS 15
>
> /* Global HWPARAMS6 Register */
> -#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
> +#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
> +#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
> +#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
> +#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
> +#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
> +#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
Keep consistency, we don't use BIT() here.
--
balbi
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