linux-kernel - Re: [PATCH 3/3] dt-bindings: Document the STM32 USB OTG DWC2 core binding

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Message-ID: <CAF3+Tqe05kXExob_62w80BBbXz6p01-WwXM1+R6ecp0JtsgviA@mail.gmail.com>
Date:	Fri, 24 Jun 2016 15:51:18 -0300
From:	Bruno Herrera <bruherrera@...il.com>
To:	Rob Herring <robh@...nel.org>
Cc:	pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, Kumar Gala <galak@...eaurora.org>,
	linux@...linux.org.uk, Maxime Coquelin <mcoquelin.stm32@...il.com>,
	johnyoun@...opsys.com, gregkh@...uxfoundation.org,
	Felipe Balbi <balbi@...nel.org>, zhangfei.gao@...aro.org,
	a.seppala@...il.com, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-usb@...r.kernel.org, alexandre.torgue@...com
Subject: Re: [PATCH 3/3] dt-bindings: Document the STM32 USB OTG DWC2 core binding

On Fri, Jun 24, 2016 at 12:41 PM, Rob Herring <robh@...nel.org> wrote:
> On Tue, Jun 21, 2016 at 11:25:49PM -0300, Bruno Herrera wrote:
>> Signed-off-by: Bruno Herrera <bruherrera@...il.com>
>> ---
>>  Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
>> index 20a68bf..79e5370 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc2.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc2.txt
>> @@ -11,6 +11,7 @@ Required properties:
>>    - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
>>    - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
>>    - snps,dwc2: A generic DWC2 USB controller with default parameters.
>> +  - st,stm32-fsotg: The DWC2 USB controller instance in STM32F4 SoCs in FS mode;
>
> This should go above snps,dwc2.
>
Ok, tks!

> What determines FS mode vs. HS?
>
Its more HW design decision.
STM32F429/439/469 has two OTG controllers, one that is FS (internal
phy) and other that is HS (but can also work in FS mode with
internal/external phy)
This bind work with both cores FS and HS working with the internal PHY.

I tested the following configurations:
1 - STM32F429I-DISCOv1 board (OTG HS working in FS mode internal PHY)
2 - STM32F469I-DISCO board (OTG FS)

I did not tested OTG HS core working in FS mode with external PHY (I2C).

>>  - reg : Should contain 1 register range (address and length)
>>  - interrupts : Should contain 1 interrupt
>>  - clocks: clock provider specifier
>> --
>> 2.7.4 (Apple Git-66)
>>