linux-kernel - Re: [PATCH v6 3/5] usb: dwc3: add phyif_utmi

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Date:	Mon, 11 Jul 2016 09:54:47 -0500
From:	Rob Herring <robh@...nel.org>
To:	Heiko Stuebner <heiko@...ech.de>
Cc:	William Wu <william.wu@...k-chips.com>, gregkh@...uxfoundation.org,
	balbi@...nel.org, linux-rockchip@...ts.infradead.org,
	briannorris@...gle.com, dianders@...gle.com,
	kever.yang@...k-chips.com, huangtao@...k-chips.com,
	frank.wang@...k-chips.com, eddie.cai@...k-chips.com,
	John.Youn@...opsys.com, linux-kernel@...r.kernel.org,
	linux-usb@...r.kernel.org, sergei.shtylyov@...entembedded.com,
	mark.rutland@....com, devicetree@...r.kernel.org
Subject: Re: [PATCH v6 3/5] usb: dwc3: add phyif_utmi_quirk

On Fri, Jul 08, 2016 at 02:33:09PM +0200, Heiko Stuebner wrote:
> Hi William,
> 
> Am Donnerstag, 7. Juli 2016, 10:54:24 schrieb William Wu:
> > Add a quirk to configure the core to support the
> > UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
> > interface is hardware property, and it's platform
> > dependent. Normall, the PHYIf can be configured
> > during coreconsultant. But for some specific usb
> > cores(e.g. rk3399 soc dwc3), the default PHYIf
> > configuration value is fault, so we need to
> > reconfigure it by software.
> > 
> > And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
> > must be set to the corresponding value according to
> > the UTMI+ PHY interface.
> > 
> > Signed-off-by: William Wu <william.wu@...k-chips.com>
> > ---
> [...]
> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > b/Documentation/devicetree/bindings/usb/dwc3.txt index 020b0e9..8d7317d
> > 100644
> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > @@ -42,6 +42,10 @@ Optional properties:
> >   - snps,dis-u2-freeclk-exists-quirk: when set, clear the
> > u2_freeclk_exists in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
> >  			a free-running PHY clock.
> > + - snps,phyif-utmi-quirk: when set core will set phyif UTMI+ interface.
> > + - snps,phyif-utmi: the value to configure the core to support a UTMI+
> > PHY +			with an 8- or 16-bit interface. Value 0 select 8-bit
> > +			interface, value 1 select 16-bit interface.
> 
> maybe
> 	snps,phyif-utmi-width = <8> or <16>;

Seems like this could be common. Any other bindings have something 
similar already? If not "utmi-width" is fine.

> 
> devicetree is about describing the hardware, not the things that get written 
> to registers :-) . The conversion from the described width to the register 
> value can easily be done in the driver.
> 
> 
> Also I don't think you need two properties for this. If the snps,phyif-utmi 
> property is specified it indicates that you want to manually set the width 
> and if it is absent you want to use the IC default. All functions reading 
> property-values indicate if the property is missing.

Agreed.

Rob