[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1468274154.2977.1.camel@infradead.org>
Date: Mon, 11 Jul 2016 14:55:54 -0700
From: Geoff Levand <geoff@...radead.org>
To: Suzuki K Poulose <suzuki.poulose@....com>,
linux-arm-kernel@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org, catalin.marinas@....com,
mark.rutland@....com, will.deacon@....com,
James Morse <james.morse@....com>
Subject: Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size
On Fri, 2016-07-08 at 12:37 +0100, Suzuki K Poulose wrote:
> On systems with mismatched i/d cache min line sizes, we need to use
> the smallest size possible across all CPUs. This will be done by fetching
> the system wide safe value from CPU feature infrastructure.
> However the some special users(e.g kexec, hibernate) would need the line
> size on the CPU (rather than the system wide), when the system wide
> feature may not be accessible. Provide another helper which will fetch
> cache line size on the current CPU.
>
Looks OK for what kexec needs.
Acked-by: Geoff Levand <geoff@...radead.org>
Powered by blists - more mailing lists