linux-kernel - [PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

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Message-Id: <1469629447-544-3-git-send-email-wxt@rock-chips.com>
Date:	Wed, 27 Jul 2016 22:24:06 +0800
From:	Caesar Wang <wxt@...k-chips.com>
To:	jic23@...nel.org, heiko@...ech.de
Cc:	devicetree@...r.kernel.org, linux-iio@...r.kernel.org,
	linux-kernel@...r.kernel.org, dianders@...omium.org,
	linux-rockchip@...ts.infradead.org, robh+dt@...nel.org,
	john@...anate.com, linux@...ck-us.net,
	linux-arm-kernel@...ts.infradead.org,
	Caesar Wang <wxt@...k-chips.com>
Subject: [PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@...k-chips.com>
---

Changes in v3:
- add Doug's reviewed tag.

Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index d02a9003..4f44d11 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -270,6 +270,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
-- 
1.9.1