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Message-ID: <CACbG30__yxUCg+ena_PpN4PTXXbeo7GWOgqKs5zLGayYKu+Adg@mail.gmail.com>
Date: Wed, 27 Jul 2016 12:04:51 -0500
From: Nilay Vaish <nilayvaish@...il.com>
To: Fenghua Yu <fenghua.yu@...el.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...e.hu>,
"H. Peter Anvin" <h.peter.anvin@...el.com>,
Tony Luck <tony.luck@...el.com>, Tejun Heo <tj@...nel.org>,
Borislav Petkov <bp@...e.de>,
Stephane Eranian <eranian@...gle.com>,
Peter Zijlstra <peterz@...radead.org>,
Marcelo Tosatti <mtosatti@...hat.com>,
David Carrillo-Cisneros <davidcc@...gle.com>,
Ravi V Shankar <ravi.v.shankar@...el.com>,
Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
Sai Prakhya <sai.praneeth.prakhya@...el.com>,
linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH 15/32] cacheinfo: Introduce cache id
On 12 July 2016 at 20:02, Fenghua Yu <fenghua.yu@...el.com> wrote:
> From: Fenghua Yu <fenghua.yu@...el.com>
>
> Each cache is described by cacheinfo and is unique in the same index
> across the platform. But there is no id for a cache. We introduce cache
> ID to identify a cache.
>
> Intel Cache Allocation Technology (CAT) allows some control on the
> allocation policy within each cache that it controls. We need a unique
> cache ID for each cache level to allow the user to specify which
> controls are applied to which cache. Cache id is a concise way to specify
> a cache.
>
> Cache id is first enabled on x86. It can be enabled on other platforms
> as well. The cache id is not necessary contiguous.
>
> Add an "id" entry to /sys/devices/system/cpu/cpu*/cache/index*/
Can you explain what index and platform mean? I think those terms are
generic in nature. May be an example on how cache ids would be
assigned to different caches would help.
--
Nilay
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