linux-kernel - Re: [PATCH V6 3/9] irqdomain: Don't set type when mapping an IRQ

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Date:	Mon, 1 Aug 2016 17:30:00 +0900
From:	Masahiro Yamada <yamada.masahiro@...ionext.com>
To:	Marc Zyngier <marc.zyngier@....com>
Cc:	Jon Hunter <jonathanh@...dia.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Jason Cooper <jason@...edaemon.net>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Stephen Warren <swarren@...dotorg.org>,
	Thierry Reding <thierry.reding@...il.com>,
	Kevin Hilman <khilman@...nel.org>,
	Geert Uytterhoeven <geert@...ux-m68k.org>,
	Grygorii Strashko <grygorii.strashko@...com>,
	Lars-Peter Clausen <lars@...afoo.de>,
	Linus Walleij <linus.walleij@...aro.org>,
	linux-tegra@...r.kernel.org, devicetree@...r.kernel.org,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V6 3/9] irqdomain: Don't set type when mapping an IRQ

Hi Marc,


2016-08-01 16:46 GMT+09:00 Marc Zyngier <marc.zyngier@....com>:
> On 01/08/16 02:28, Masahiro Yamada wrote:
>> 2016-07-29 17:10 GMT+09:00 Marc Zyngier <marc.zyngier@....com>:
>>> On 29/07/16 04:53, Masahiro Yamada wrote:
>>>> Hi.
>>>>
>>>>
>>>> I noticed my board would not work any more
>>>> when pulling recent updates.
>>>>
>>>>
>>>> I did "git-bisect" and I found the following commit is it.
>>>
>>> It would help if you did post the log showing the failure.
>>>
>>> What if you apply the following patch:
>>>
>>> https://git.kernel.org/cgit/linux/kernel/git/maz/arm-platforms.git/diff/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi?h=timers/level-trigger&id=95e1fd920fcadce81626cfa9bd6af1a361f17e58
>>>
>>
>> Hi Mark,
>>
>> Yes, it worked.
>>
>> But I did not understand why you changed the 3rd cell to 0xf08.
>>
>>
>> The binding of arm,gic-v3.txt says as follows:
>>
>>
>>   The 3rd cell is the flags, encoded as follows:
>>         bits[3:0] trigger type and level flags.
>>                 1 = edge triggered
>>                 4 = level triggered
>>
>>
>> Only 1 and 4 are defined for the bits[3:0].
>
> Ah, I didn't realize you were using GICv3.
>
> If you look at the documentation for the A72 timers:
> http://infocenter.arm.com/help/topic/com.arm.doc.100095_0003_05_en/way1382454511590.html
>
> You'll notice that all timers have an active-low output. Switching to
> "level triggered" fixes the issue in general.
>
>> 0xf04 worked, too.
>>
>> Which is correct?
>
> None of them. 0x04 is the correct answer (as we don't encode the
> affinity in the 3rd cell.


Thank you!





-- 
Best Regards
Masahiro Yamada