linux-kernel - Re: [PATCH v2 2/2] arm64: dts: Fix broken architected timer interrupt trigger

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Message-ID: <CAK7LNARVw+mDhHT2+WjDtHpBvsxauUQpRCJeNLrQxrj0Oo=hrQ@mail.gmail.com>
Date:	Mon, 1 Aug 2016 19:00:50 +0900
From:	Masahiro Yamada <yamada.masahiro@...ionext.com>
To:	Marc Zyngier <marc.zyngier@....com>
Cc:	Thomas Gleixner <tglx@...utronix.de>,
	Daniel Lezcano <daniel.lezcano@...aro.org>, arm@...nel.org,
	Duc Dang <dhdang@....com>, Carlo Caione <carlo@...lessm.com>,
	Michal Simek <michal.simek@...inx.com>,
	Krzysztof Kozlowski <k.kozlowski@...sung.com>,
	Dinh Nguyen <dinguyen@...nsource.altera.com>,
	Mark Rutland <marc.rutland@....com>,
	Jon Hunter <jonathanh@...dia.com>,
	Carlo Caione <carlo@...one.org>,
	Kevin Hilman <khilman@...libre.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	Ray Jui <rjui@...adcom.com>,
	Scott Branden <sbranden@...adcom.com>,
	Kukjin Kim <kgene@...nel.org>,
	Jason Cooper <jason@...edaemon.net>,
	Andrew Lunn <andrew@...n.ch>,
	Gregory Clement <gregory.clement@...e-electrons.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
	Sören Brinkmann <soren.brinkmann@...inx.com>,
	Tirumalesh Chalamarla <tchalamarla@...ium.com>,
	Jan Glauber <jglauber@...ium.com>,
	Hou Zhiqiang <B48286@...escale.com>,
	Wenbin Song <Wenbin.Song@...escale.com>,
	Yuan Yao <yao.yuan@....com>, Liu Gang <Gang.Liu@....com>,
	Mingkai Hu <Mingkai.Hu@...escale.com>,
	Rajesh Bhagat <rajesh.bhagat@...escale.com>,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	linux-amlogic@...ts.infradead.org,
	Broadcom Kernel Feedback List 
	<bcm-kernel-feedback-list@...adcom.com>,
	linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v2 2/2] arm64: dts: Fix broken architected timer interrupt trigger

2016-08-01 18:54 GMT+09:00 Marc Zyngier <marc.zyngier@....com>:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring the interrupt
> to be edge triggered. A quick look at the TRM for the corresponding ARM
> CPUs clearly shows that this is wrong, and I've corrected those.
> For non-ARM designs (and in the absence of a publicly available TRM),
> I've made them active low as well, which can't be completely wrong
> as the GIC cannot disinguish between level low and level high.
>
> The respective maintainers are of course welcome to prove me wrong.
>
> While I was at it, I took the liberty to fix a couple of related issue,
> such as some spurious affinity bits on ThunderX, and their complete
> absence on ls1043a (both of which seem to be related to copy-pasting
> from other DTs).
>
> Acked-by: Duc Dang <dhdang@....com>
> Acked-by: Carlo Caione <carlo@...lessm.com>
> Acked-by: Michal Simek <michal.simek@...inx.com>
> Acked-by: Krzysztof Kozlowski <k.kozlowski@...sung.com>
> Acked-by: Dinh Nguyen <dinguyen@...nsource.altera.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@....com>
> ---
>  arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi    | 8 ++++----
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi          | 8 ++++----
>  arch/arm64/boot/dts/apm/apm-storm.dtsi               | 8 ++++----
>  arch/arm64/boot/dts/broadcom/ns2.dtsi                | 8 ++++----
>  arch/arm64/boot/dts/cavium/thunder-88xx.dtsi         | 8 ++++----
>  arch/arm64/boot/dts/exynos/exynos7.dtsi              | 8 ++++----
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi       | 8 ++++----
>  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi       | 8 ++++----
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 8 ++++----
>  arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----


For uniphier-ph1-ld20.dtsi,

Acked-by: Masahiro Yamada <yamada.masahiro@...ionext.com>


Thank you!!


-- 
Best Regards
Masahiro Yamada