| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Mon, 1 Aug 2016 06:25:17 -0700
From: tip-bot for Marc Zyngier <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: jason@...edaemon.net, B48286@...escale.com, f.fainelli@...il.com,
sebastian.hesselbarth@...il.com, tchalamarla@...ium.com,
rajesh.bhagat@...escale.com, Wenbin.Song@...escale.com,
rjui@...adcom.com, marc.zyngier@....com, andrew@...n.ch,
michal.simek@...inx.com, tglx@...utronix.de, khilman@...libre.com,
yamada.masahiro@...ionext.com, Gang.Liu@....com,
jglauber@...ium.com, Mingkai.Hu@...escale.com,
linux-kernel@...r.kernel.org, mingo@...nel.org,
jonathanh@...dia.com, yao.yuan@....com, dhdang@....com,
hpa@...or.com, dinguyen@...nsource.altera.com,
daniel.lezcano@...aro.org, kgene@...nel.org, carlo@...one.org,
marc.rutland@....com, gregory.clement@...e-electrons.com,
sbranden@...adcom.com
Subject: [tip:timers/urgent] clocksource/arm_arch_timer: Force per-CPU
interrupt to be level-triggered
Commit-ID: 1604dd8aa5827c71b1fdc302c53b678dfa20c6fc
Gitweb: http://git.kernel.org/tip/1604dd8aa5827c71b1fdc302c53b678dfa20c6fc
Author: Marc Zyngier <marc.zyngier@....com>
AuthorDate: Mon, 1 Aug 2016 10:54:15 +0100
Committer: Thomas Gleixner <tglx@...utronix.de>
CommitDate: Mon, 1 Aug 2016 15:17:45 +0200
clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered
The ARM architected timer produces level-triggered interrupts (this
is mandated by the architecture). Unfortunately, a number of
device-trees get this wrong, and expose an edge-triggered interrupt.
Until now, this wasn't too much an issue, as the programming of the
trigger would fail (the corresponding PPI cannot be reconfigured),
and the kernel would be happy with this. But we're about to change
this, and trust DT a lot if the driver doesn't provide its own
trigger information. In that context, the timer breaks badly.
While we do need to fix the DTs, there is also some userspace out
there (kvmtool) that generates the same kind of broken DT on the
fly, and that will completely break with newer kernels.
As a safety measure, and to keep buggy software alive as well as
buying us some time to fix DTs all over the place, let's check
what trigger configuration has been given us by the firmware.
If this is not a level configuration, then we know that the
DT/ACPI configuration is bust, and we pick some defaults which
won't be worse than the existing setup.
Signed-off-by: Marc Zyngier <marc.zyngier@....com>
Cc: Andrew Lunn <andrew@...n.ch>
Cc: Liu Gang <Gang.Liu@....com>
Cc: Mark Rutland <marc.rutland@....com>
Cc: Masahiro Yamada <yamada.masahiro@...ionext.com>
Cc: Wenbin Song <Wenbin.Song@...escale.com>
Cc: Mingkai Hu <Mingkai.Hu@...escale.com>
Cc: Florian Fainelli <f.fainelli@...il.com>
Cc: Kevin Hilman <khilman@...libre.com>
Cc: Daniel Lezcano <daniel.lezcano@...aro.org>
Cc: Michal Simek <michal.simek@...inx.com>
Cc: Jon Hunter <jonathanh@...dia.com>
Cc: arm@...nel.org
Cc: bcm-kernel-feedback-list@...adcom.com
Cc: linux-arm-kernel@...ts.infradead.org
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
Cc: Jason Cooper <jason@...edaemon.net>
Cc: Ray Jui <rjui@...adcom.com>
Cc: "Hou Zhiqiang" <B48286@...escale.com>
Cc: Tirumalesh Chalamarla <tchalamarla@...ium.com>
Cc: linux-samsung-soc@...r.kernel.org
Cc: Yuan Yao <yao.yuan@....com>
Cc: Jan Glauber <jglauber@...ium.com>
Cc: Gregory Clement <gregory.clement@...e-electrons.com>
Cc: linux-amlogic@...ts.infradead.org
Cc: soren.brinkmann@...inx.com
Cc: Rajesh Bhagat <rajesh.bhagat@...escale.com>
Cc: Scott Branden <sbranden@...adcom.com>
Cc: Duc Dang <dhdang@....com>
Cc: Kukjin Kim <kgene@...nel.org>
Cc: Carlo Caione <carlo@...one.org>
Cc: Dinh Nguyen <dinguyen@...nsource.altera.com>
Link: http://lkml.kernel.org/r/1470045256-9032-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
drivers/clocksource/arm_arch_timer.c | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 28bce3f..5770054 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -8,6 +8,9 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+
+#define pr_fmt(fmt) "arm_arch_timer: " fmt
+
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/device.h>
@@ -370,16 +373,33 @@ static bool arch_timer_has_nonsecure_ppi(void)
arch_timer_ppi[PHYS_NONSECURE_PPI]);
}
+static u32 check_ppi_trigger(int irq)
+{
+ u32 flags = irq_get_trigger_type(irq);
+
+ if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
+ pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
+ pr_warn("WARNING: Please fix your firmware\n");
+ flags = IRQF_TRIGGER_LOW;
+ }
+
+ return flags;
+}
+
static int arch_timer_starting_cpu(unsigned int cpu)
{
struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
+ u32 flags;
__arch_timer_setup(ARCH_CP15_TIMER, clk);
- enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], 0);
+ flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
+ enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
- if (arch_timer_has_nonsecure_ppi())
- enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
+ if (arch_timer_has_nonsecure_ppi()) {
+ flags = check_ppi_trigger(arch_timer_ppi[PHYS_NONSECURE_PPI]);
+ enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], flags);
+ }
arch_counter_set_user_access();
if (evtstrm_enable)
Powered by blists - more mailing lists