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Message-ID: <CAMzpN2jtqpEPdAwDgx3-VwhCC9Q9yDir5tbYXKGZnzQiK45d0g@mail.gmail.com>
Date:	Sun, 14 Aug 2016 08:50:57 -0400
From:	Brian Gerst <brgerst@...il.com>
To:	Andy Lutomirski <luto@...capital.net>
Cc:	Josh Poimboeuf <jpoimboe@...hat.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...nel.org>,
	"H . Peter Anvin" <hpa@...or.com>, X86 ML <x86@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Steven Rostedt <rostedt@...dmis.org>,
	Kees Cook <keescook@...omium.org>,
	Peter Zijlstra <peterz@...radead.org>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Byungchul Park <byungchul.park@....com>,
	Nilay Vaish <nilayvaish@...il.com>
Subject: Re: [PATCH v3 45/51] x86: remove 64-byte gap at end of irq stack

On Sun, Aug 14, 2016 at 3:52 AM, Andy Lutomirski <luto@...capital.net> wrote:
> On Fri, Aug 12, 2016 at 7:29 AM, Josh Poimboeuf <jpoimboe@...hat.com> wrote:
>> There has been a 64-byte gap at the end of the irq stack for at least 12
>> years.  It predates git history, and I can't find any good reason for
>> it.  Remove it.  What's the worst that could happen?
>
> I can't think of any reason this would matter.
>
> For that matter, do you have any idea why irq_stack_union is a union
> or why we insist on sticking it at %gs:0?  Sure, the *canary* needs to
> live at a fixed offset (because GCC is daft, sigh), but I don't see
> what that has to do with the rest of the IRQ stack.
>
> --Andy

Because the IRQ stack requires page alignment so it was convenient to
put it at the start of the per-cpu area.  I don't think at the time I
wrote this there was specific support for page-aligned objects in
per-cpu memory.  Since stacks grow down, it was tolerable to reserve a
few bytes at the bottom for the canary.

What would be great is if we could leverage the new GCC plugin tools
to reimplement stack protector in a manner that is more compatible
with the kernel environment.  It would make the stack canary a true
per-cpu variable instead of the hard-coded TLS-based location it is
now.  That would make 64-bit be able to use normal delta per-cpu
offsets instead of zero-based, and would allow 32-bit to always do
lazy GS.

--
Brian Gerst

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