linux-kernel - Re: [PATCH v10 03/11] dmaengine: dw: override LLP support if asked in platform data

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Message-ID: <1471353666.1562.3.camel@synopsys.com>
Date:	Tue, 16 Aug 2016 13:21:06 +0000
From:	Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
To:	"andriy.shevchenko@...ux.intel.com" 
	<andriy.shevchenko@...ux.intel.com>
CC:	"ismo.puustinen@...el.com" <ismo.puustinen@...el.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"vinod.koul@...el.com" <vinod.koul@...el.com>,
	"heikki.krogerus@...ux.intel.com" <heikki.krogerus@...ux.intel.com>,
	"Eugeniy.Paltsev@...opsys.com" <Eugeniy.Paltsev@...opsys.com>,
	"linux-snps-arc@...ts.infradead.org" 
	<linux-snps-arc@...ts.infradead.org>,
	"dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>,
	"linux-serial@...r.kernel.org" <linux-serial@...r.kernel.org>,
	"gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
	"peter@...leysoftware.com" <peter@...leysoftware.com>,
	"pure.logic@...us-software.ie" <pure.logic@...us-software.ie>
Subject: Re: [PATCH v10 03/11] dmaengine: dw: override LLP support if asked
 in platform data

On Fri, 2016-08-12 at 19:01 +0300, Andy Shevchenko wrote:
> There are at least two known devices, e.g. DMA controller found on
> ARC AXS101
> SDP board, that have LLP register and no multi block transfer support
> at the
> same time.
> 
> Override autodetection by user provided data.
> 
> Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> ---
>  drivers/dma/dw/core.c                | 6 +-----
>  include/linux/platform_data/dma-dw.h | 2 ++
>  2 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
> index 80e7421..da18b18 100644
> --- a/drivers/dma/dw/core.c
> +++ b/drivers/dma/dw/core.c
> @@ -1571,11 +1571,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
>  				(dwc_params >> DWC_PARAMS_MBLK_EN &
> 0x1) == 0;
>  		} else {
>  			dwc->block_size = pdata->block_size;
> -
> -			/* Check if channel supports multi block
> transfer */
> -			channel_writel(dwc, LLP,
> DWC_LLP_LOC(0xffffffff));
> -			dwc->nollp = DWC_LLP_LOC(channel_readl(dwc,
> LLP)) == 0;
> -			channel_writel(dwc, LLP, 0);
> +			dwc->nollp = pdata->is_nollp;
>  		}
>  	}
>  
> diff --git a/include/linux/platform_data/dma-dw.h
> b/include/linux/platform_data/dma-dw.h
> index 4636c93..5f0e11e 100644
> --- a/include/linux/platform_data/dma-dw.h
> +++ b/include/linux/platform_data/dma-dw.h
> @@ -40,6 +40,7 @@ struct dw_dma_slave {
>   * @is_private: The device channels should be marked as private and
> not for
>   *	by the general purpose DMA channel allocator.
>   * @is_memcpy: The device channels do support memory-to-memory
> transfers.
> + * @is_nollp: The device channels does not support multi block
> transfers.
>   * @chan_allocation_order: Allocate channels starting from 0 or 7
>   * @chan_priority: Set channel priority increasing from 0 to 7 or 7
> to 0.
>   * @block_size: Maximum block size supported by the controller
> @@ -51,6 +52,7 @@ struct dw_dma_platform_data {
>  	unsigned int	nr_channels;
>  	bool		is_private;
>  	bool		is_memcpy;
> +	bool		is_nollp;
>  #define CHAN_ALLOCATION_ASCENDING	0	/* zero to seven
> */
>  #define CHAN_ALLOCATION_DESCENDING	1	/* seven to zero
> */
>  	unsigned char	chan_allocation_order;

Looks good to me.
Reviewed-by: Eugeniy Platsev <Eugeniy.Paltsev@...opsys.com>