linux-kernel - [PATCH v2] x86/tsc: Set X86_FEATURE_TSC_RELIABLE to skip refined calibration

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Message-ID: <20160816174240.GA33372@worksta>
Date:	Tue, 16 Aug 2016 10:42:40 -0700
From:	Bin Gao <bin.gao@...ux.intel.com>
To:	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, x86@...nel.org
Cc:	linux-kernel@...r.kernel.org, bin.gao@...el.com
Subject: [PATCH v2] x86/tsc: Set X86_FEATURE_TSC_RELIABLE to skip refined
 calibration

On some newer Intel x86 processors/SoCs the TSC frequency can be directly
calculated by factors read from specific MSR registers or from a cpuid
leaf (0x15). TSC frequency calculated by native msr/cpuid is absolutely
accurate so we should always skip calibrating TSC aginst another clock,
e.g. PIT, HPET, etc. So we want to skip the refined calibration by setting
the X86_FEATURE_TSC_RELIABLE flag. Existing code setting the flag by
set_cpu_cap() doesn't work as the flag is cleared later in identify_cpu().
A cpu caps flag is not cleared only if it's set by setup_force_cpu_cap().
This patch converted set_cpu_cap() to setup_force_cpu_cap() to ensure
refined calibration is skipped.

We had a test on Intel CherryTrail platform: the 24 hours time drift is
3.6 seconds if refined calibration was not skipped while the drift is less
than 0.6 second when refined calibration was skipped.

Correctly setting the X86_FEATURE_TSC_RELIABLE flag also guarantees TSC is
not monitored by timekeeping watchdog because on most of these system TSC
is the only reliable clocksource. HPET, for instance, works but may not
be reliable. So kernel may report a physically reliable TSC is not reliable
just because a physically not reliable HPET is acting as timekeeping
watchdog.

Signed-off-by: Bin Gao <bin.gao@...el.com>
---
Changes in v2:
 - Set X86_FEATURE_TSC_RELIABLE for cpuid case
 - Patch description change
 arch/x86/kernel/tsc.c               | 1 +
 arch/x86/kernel/tsc_msr.c           | 2 ++
 arch/x86/platform/intel-mid/mfld.c  | 2 +-
 arch/x86/platform/intel-mid/mrfld.c | 2 +-
 4 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 78b9cb5..e26f86b 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -696,6 +696,7 @@ unsigned long native_calibrate_tsc(void)
 		}
 	}

+	setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
 	return crystal_khz * ebx_numerator / eax_denominator;
 }

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 0fe720d..42335fb 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -100,5 +100,7 @@ unsigned long cpu_khz_from_msr(void)
 #ifdef CONFIG_X86_LOCAL_APIC
 	lapic_timer_frequency = (freq * 1000) / HZ;
 #endif
+
+	setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
 	return res;
 }
diff --git a/arch/x86/platform/intel-mid/mfld.c b/arch/x86/platform/intel-mid/mfld.c
index 1eb47b6..c75e7a4 100644
--- a/arch/x86/platform/intel-mid/mfld.c
+++ b/arch/x86/platform/intel-mid/mfld.c
@@ -50,7 +50,7 @@ static unsigned long __init mfld_calibrate_tsc(void)
 	pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
 	lapic_timer_frequency = fsb * 1000 / HZ;
 	/* mark tsc clocksource as reliable */
-	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
+	setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);

 	return fast_calibrate;
 }
diff --git a/arch/x86/platform/intel-mid/mrfld.c b/arch/x86/platform/intel-mid/mrfld.c
index 59253db..126330c 100644
--- a/arch/x86/platform/intel-mid/mrfld.c
+++ b/arch/x86/platform/intel-mid/mrfld.c
@@ -79,7 +79,7 @@ static unsigned long __init tangier_calibrate_tsc(void)
 			lapic_timer_frequency);

 	/* mark tsc clocksource as reliable */
-	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
+	setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);

 	return fast_calibrate;
 }
-- 
1.9.1