linux-kernel - Re: [PATCH] arm64: dts: rockchip: fix the address map for WDT0 and WDT1

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Message-ID: <607537bf-1c49-d7e0-ead9-8c1e6164e44e@rock-chips.com>
Date:   Fri, 26 Aug 2016 17:41:28 +0800
From:   Shawn Lin <shawn.lin@...k-chips.com>
To:     Xing Zheng <zhengxing@...k-chips.com>,
        linux-rockchip@...ts.infradead.org
Cc:     shawn.lin@...k-chips.com, huangtao@...k-chips.com,
        Mark Rutland <mark.rutland@....com>,
        Elaine Zhang <zhangqing@...k-chips.com>,
        Heiko Stuebner <heiko@...ech.de>, devicetree@...r.kernel.org,
        Catalin Marinas <catalin.marinas@....com>,
        Brian Norris <briannorris@...omium.org>,
        Will Deacon <will.deacon@....com>, dianders@...omium.org,
        linux-kernel@...r.kernel.org,
        Masahiro Yamada <yamada.masahiro@...ionext.com>,
        Rob Herring <robh+dt@...nel.org>,
        David Wu <david.wu@...k-chips.com>, jay.xu@...k-chips.com,
        linux-arm-kernel@...ts.infradead.org,
        Caesar Wang <wxt@...k-chips.com>
Subject: Re: [PATCH] arm64: dts: rockchip: fix the address map for WDT0 and
 WDT1

On 2016/8/26 14:22, Xing Zheng wrote:
> Dues to incorrect description in the TRM, the WDTs base address
> should be fixed and swap them like this:
> WDT0 - 0xff848000
> WDT1 - 0xff840000
>
> And, it is right that only WDT0 can generate global software reset.
> We will update the TRM to fix it.
>
> Signed-off-by: Xing Zheng <zhengxing@...k-chips.com>
> ---
>
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index bc86e8c..f0f52c1 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -1002,9 +1002,9 @@
>  		};
>  	};
>
> -	watchdog@...40000 {
> +	watchdog@...48000 {

Just a nit, should we mark this explicitly as "watchdog0" ?
I still need to look up for which wdt you are using.:)

>  		compatible = "snps,dw-wdt";
> -		reg = <0x0 0xff840000 0x0 0x100>;
> +		reg = <0x0 0xff848000 0x0 0x100>;
>  		clocks = <&cru PCLK_WDT>;
>  		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
>  	};
>


-- 
Best Regards
Shawn Lin